2026-07-14
4 items 112 entities 180 connections
Processed 26 entities and 46 relations.
VCS MathSAT5 Yices Z3 Constrained Random Verification Constraint Solver Conjunctive Normal Form (CNF) SAT Solving Satisfiability Modulo Theories (SMT) Sudoku Constraint Solving Object-Oriented Constraint Composition (OOP) Flat Constraint Composition (FLAT) Clausal Reduction Optimization Latin Square SystemVerilog Sudoku Solver SystemVerilog Test Bench SMT2 Constraint Language Input Perl Jeremy Ridgeway Avago Technologies Synopsys Parasitic Literals Implication Operator in Constraints If-Else Constraint Construct Constant vs Variable in Constraint Performance of a SystemVerilog Sudoku Solver with VCS
Processed 18 entities and 24 relations.
Stimulus Generation Constrained-Random Verification Direct Tests Randomized Tests SystemVerilog Constraints Constraint Solver rand Modifier randc Modifier Constraint Block randomize() Method Implication Constraint Inline Constraint constraint_mode() inside Operator Corner Case Coverage UVM BusTransaction Class Packet Class
Processed 55 entities and 95 relations.
Functional Verification ASIC Design SystemVerilog Testbench Universal Verification Methodology (UVM) Coverage-Directed Generation (CDG) Stimulus Generation Constraint-Based Random Test Generation RTL (Register Transfer Level) Genetic Algorithm (GA) Cell-Based Genetic Algorithm (CGA) Feedback-Adjusted Markov Model Recurrent Neural Network (RNN) Bayesian Network Reinforcement Learning (RL) Graph Neural Network (GNN) Static Code Analysis Natural Language Processing (NLP) Constraint Logic Programming (CLP) Biased-Random Simulation Pseudo-Random Generator (PRG) Constraint Optimization Hierarchical Learning Explainable AI (XAI) Formal Verification Transfer Learning StressTest Unified Coverage Database (UCDB) Coverage Closure Microprocessor Verification Device Under Verification (DUV) State Space Explosion Reward Shaping Assertion Coverage Abstract State Machine (ASM) 8051 Soft Core Processor Bhavin Shah Wagner, Ilya Fajcik, Martin Fine, S. Ziv, A. Goloubeva, O. Samarah, et al. Habibi, Ali Tahar, Sofiène Zeng, Z. AI based SystemVerilog TB generation Microprocessor Verification via Feedback-Adjusted Markov Models Automation of Processor Verification Using Recurrent Neural Networks Automation and Optimization of Coverage-driven Verification A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage Automatic Generation of Validation Stimuli for Application-Specific Processors Design and Verification of SystemC Transaction-Level Models Coverage Directed Test Generation for Functional Verification Using Bayesian Networks Techvulcan Inc IEEE Zeng, Z.