Boolean Satisfiability
ConceptBoolean Satisfiability (SAT) is the decision problem of determining whether a Boolean formula admits a satisfying assignment. In the provided evidence SAT is treated both as the solving engine behind formal hardware verification techniques such as SAT-based Bounded Model Checking and Interval Property Checking, and as the foundation for richer SAT-related problems including uniform witness generation, model counting, and the computation of unsatisfiable cores and minimal unsatisfiable subformulas.
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Overview
Boolean Satisfiability, abbreviated SAT, is the problem of deciding whether a Boolean formula admits an assignment that makes it evaluate to true. In the provided evidence, SAT appears in three main roles: (1) as the solving engine at the core of SAT-based formal hardware verification techniques, (2) as the foundation for SAT-related extensions such as uniform witness generation and model counting, and (3) as the conceptual origin of related problems such as unsatisfiable-core and minimal unsatisfiable subformula computation, which are reused in adjacent domains such as diagnosing over-constrained constraint-based random simulation.[C1][C2][C3][C4][C8]
Use in formal hardware verification
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