Boolean Satisfiability
ConceptBoolean Satisfiability (SAT) is the decision problem of determining whether a Boolean formula has a satisfying assignment. In the provided evidence, SAT plays a central role in formal hardware verification (as the solving engine behind SAT-based Bounded Model Checking and Interval Property Checking) and is the source of related sub-problems such as unsatisfiable-core and minimal-unsatisfiable-subformula computation that arise in diagnosing over-constrained problems.
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Overview
Boolean Satisfiability, abbreviated SAT, is the problem of deciding whether a Boolean formula admits an assignment that makes it evaluate to true. In the provided evidence, SAT appears in two main roles: (1) as the solving engine at the core of SAT-based formal hardware verification techniques, and (2) as the conceptual origin of related problems such as unsatisfiable-core and minimal unsatisfiable subformula computation, which are reused in adjacent domains such as diagnosing over-constrained constraint-based random simulation.[C1][C2]
Use in formal hardware verification
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