Binary Search Fault-Detected Cycle

Binary Search Fault-Detected Cycle (BFTC)

Concept

The Binary Search Fault-Detected Cycle (BFTC) is a coarse-grained run-cycle index at which a fault first becomes observable through node counter values during an exponentially stepped binary search performed at 1024-clock-cycle increments. BFTC values bracket the latency range in which a fault is detected and serve as the starting points for a subsequent single-cycle incremental sweep that pinpoints the exact Incremental Search Fault-Detected Cycle (IFTC) used in the Fault-Run-Cycle-Based FTBE methodology.

First seen 7/13/2026

Last seen 7/13/2026

Evidence 2 chunks

Wiki v1

WIKI

Definition

A Binary Search Fault-Detected Cycle (BFTC) is the run cycle, expressed in increments of 1024 clock cycles, at which a fault is first detected during the binary-search stage of identifying Fault-Observable Run Cycles (IFTCs) on a target processor. It is defined as the upper-bound cycle of the binary search interval for which the fault remains undetected at the lower bound but is detected at the upper bound. Each BFTC is then refined by an incremental sweep into an exact-cycle Incremental Search Fault-Detected Cycle (IFTC) ^[1].

Generation Procedure

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RELATIONSHIPS

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Fault-Run-Cycle-Based FTBE ← uses 90% 1e

The RCBE generation uses binary search to find fault-detected cycles.

LINKED ENTITIES

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Fault-Run-Cycle-Based FTBE USES Extracted graph relationship

CITATIONS

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[1] A Binary Search Fault-Detected Cycle (BFTC) is the run cycle at 1024-cycle increments where a fault is first detected during the binary-search stage of identifying Fault-Observable Run Cycles. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[2] The binary search spans from 1024 to 6,717,440 clock cycles in 1024-cycle increments, requiring 13 iterations per fault. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[3] AES BFTCs on Potato are tabulated by fault type, with the highest-latency detection at cycle 6,078,464 for delay faults. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[4] Each BFTC is passed to an incremental sweep starting at BFTC − 1024 and stepping by single clock cycles to yield the exact Incremental Search Fault-Detected Cycle (IFTC). An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

[5] The BFTC and IFTC identification is the first colour-coded segment of the RCBE generation flowchart, followed by μP state extraction and binary creation for fault-triggered state replication. An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor