2026-06-21
4 items 195 entities 197 connections
Processed 23 entities and 22 relations.
armshaker processor fuzzing hidden instructions undefined instruction exception exhaustive instruction space search SIGILL Armv8-A ISA A64 instruction set A32 instruction set T32 instruction set ptrace-based instruction execution multiprocessing fuzzing random register value initialization instruction mask-based targeted fuzzing libopcodes disassembler Capstone disassembler sandsifter Christopher Domas condition code matching undocumented instructions armshaker.py front-end fuzzer back-end shell_frontend.sh
Processed 39 entities and 55 relations.
Suresh Chips and Semiconductor RISC-V Register Transfer Level (RTL) Instruction Set Architecture (ISA) Parameterization XLEN Pipeline Depth Branch Predictor Branch History Table (BHT) Branch Target Buffer (BTB) Cache Associativity AXI Bus Interface AHB Bus Interface TL-UL Bus Interface Physical Memory Protection (PMP) Smepmp Privilege Modes Cache Coherency Protocol RISC-V Weak Memory Ordering (RVWMO) Register Bypassing Speculative Execution Non-Blocking Cache Instruction Set Simulator (ISS) Spike QEMU Universal Verification Methodology (UVM) cocotb Design Under Test (DUT) Constrained Random Verification (CRV) Formal Verification (FV) SystemVerilog Assertions (SVA) UVM Sequence Layer Bus Functional Model (BFM) Scoreboard Verification IP (VIP) riscv_core RTL Module FPU (Floating Point Unit) Integer Multiply/Divide Unit Interrupt Controller
Processed 43 entities and 46 relations.
CHERI RISC-V CHERI-RISC-V capability pointer memory safety buffer overflow use-after-free tagged memory capability bounds capability permissions capability tag bit monotonicity hybrid mode virtual prototype transaction-level modeling RTL simulation emulation QEMU SystemC design space exploration RISC-V VP++ CHERI-RISC-V VP++ instruction set simulator TLM tag extension virtual memory management TLB TestRIG Direct Instruction Injection RISC-V Formal Interface CHERI RISC-V Sail model RVVTS CheriBSD instruction overhead benchmark workload security analysis Manfred Schlägl Andreas Hinterdorfer Daniel Große Institute for Complex Systems A RISC-V CHERI VP: Enabling System-Level Evaluation of the Capability-Based CHERI Architecture early software development RISC-V Vector Extension interpreter-based ISS
Processed 90 entities and 74 relations.
RISC-V Functional Verification Formal Verification Coverage-Driven Verification Directed Tests Random Tests Constrained Random Stimulus Self-Checking Tests Instruction Set Simulator (ISS) Golden Reference Model Trace Log File Comparison Sync-Lock-Step Compare Async-Lock-Step Compare Instruction Stream Generator (ISG) Error Modelling Compliance Testing Signature-Based Test RTL Simulation Software-Based Self-Test (SBST) Burn-In Programs Benchmark Testing Hello World Test Verification Plan Functional Coverage Code Coverage Model Checking Theorem Proving Equivalence Checking Assertions Genetic Algorithm-Based Test Generation Binary Decision Diagrams (BDDs) Pseudo-Random Test Generation Cross-Level Testing RISC-V Verification Interface (RVVI) UVM (Universal Verification Methodology) OVM (Open Verification Methodology) SystemVerilog Testbench riscvOVPsim riscvOVPsimPlus ImperasDV riscv-formal RISC-V Torture Test Generator Shakti AAPG (Automated Assembly Program Generator) Google riscv-dv / COREV-DV riscvISACOV Jasper Formal Verification TestRIG Verilator SyDeKick PVS (Prototype Verification System) Chipyard μGP (Micro Genetic Program) RVVI-Trace RVVI-API RVVI-VVP (Virtual Verification Peripherals) Verification IP (VIP) Design Under Test (DUT) Instruction Set Architecture (ISA) Hardware Description Language (HDL) RTL (Register Transfer Level) FPGA Prototyping Emulation RISC-V International University of California, Berkeley Imperas OpenHW Group Cadence Siemens EDA Synopsys Google Chloe Tain Savita Patil Hussain Al-Asaad CORE-V-VERIF Testbench CV32E40P Rocket Core BOOM (Berkeley Out-of-Order Machine) Ibex (Zero-RISCV) CVA6 (Ariane) VexRiscv PicoRV32 SweRV (VeeR EL2) PULPino Hardware Design Verification (HW DV) Testbench Program Counter (PC) Monitoring Sail Specification Language CHERI Security Extension Chisel HDL CoreMark Benchmark