Condition code matching

In the AArch32 execution state, every instruction begins with a four-bit condition code field. The processor evaluates this field against the current condition flags in the CPSR (Current Program Status Register) and only executes the instruction when the condition holds. When the condition does not hold, the instruction is treated as a NOP.

When fuzzing for hidden or undocumented instructions on real hardware, this default behavior can produce a large number of false positives. Some Armv8-A implementations execute undefined instructions whose condition code does not match the current flags as silent NOPs, rather than raising an undefined-instruction exception. This is documented as implementation-defined behavior in section G1.16.1 of the Arm Architecture Reference Manual (DDI0487).