A32 instruction set

Concept

A32 (also called ARM32) is a 32-bit fixed-length instruction set used in the AArch32 execution state of the ARM architecture. It is one of three AArch32 instruction sets (alongside T32/Thumb-2 and T16/Thumb-1) and is supported across ARMv5 through ARMv8. A32 has been studied as a target for differential testing (Examiner) and hidden-instruction fuzzing (armshaker) of Armv8-A hardware and emulators.

First seen 6/7/2026

Last seen 6/21/2026

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A32 instruction set

Overview

A32, also referred to as ARM32, is a 32-bit fixed-length instruction set used in the AArch32 execution state of the ARM architecture. It is one of the three instruction sets defined for AArch32 mode, alongside T32 (Thumb-2, mixed 16/32-bit) and T16 (Thumb-1, 16-bit).

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RELATIONSHIPS

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Examiner ← uses 100% 2e

Examiner generates test cases covering A32 instruction set encodings.

armshaker ← uses 100% 1e

armshaker can fuzz the A32 instruction set when compiled with a 32-bit toolchain.

Armv8-A ISA part of → 100% 1e

A32 is one of the three instruction sets that make up the Armv8-A ISA.

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CITATIONS

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[1] A32 (ARM32) is a 32-bit fixed-length instruction set used in the AArch32 execution state of the ARM architecture. Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM

[2] A32 is one of three AArch32 instruction sets (with T32/Thumb-2 and T16/Thumb-1) and is supported across ARMv5, ARMv6, ARMv7, and ARMv8. Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM

[3] The combined A32+T32+T16 instruction set contains 489 instructions; A32 alone accounts for 550 instruction encodings in the Examiner evaluation. Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM

[4] Examiner's A32 test-case generator produced 870,221 instruction streams covering 550 encodings, 481 instructions, and 4,718 constraints. Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM

[5] armshaker is an Armv8-A processor fuzzer that exhaustively searches for hidden instructions across A64, A32, and T32 by detecting the absence of SIGILL on undefined encodings. frestr/armshaker

[6] On AArch32 builds of armshaker, A32 is the default instruction set and T32 is selected with -t; on AArch64 builds A64 is default, with cross-compilation to fuzz A32/T32. frestr/armshaker

[7] armshaker's README documents example A32/T32 invocations for checking hidden VMUL and VQDMULL instructions in QEMU. frestr/armshaker

[8] The large number of apparent hidden A32 instructions reported by armshaker can stem from processors executing undefined instructions with unmatched condition codes as NOPs (Armv8 ARM section G1.16.1), mitigated by the -c option. frestr/armshaker