Armv8-A ISA

Concept

Armv8-A is an ARM architecture profile that defines a family of instruction sets (A64, A32, and T32) supported under AArch64 and AArch32 execution states, and is used in both commercial hardware and academic/experimental toolchains for ISA-level analysis and verification.

First seen 6/21/2026

Last seen 6/21/2026

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Armv8-A ISA

Overview

Armv8-A is an ARM architecture profile whose Instruction Set Architecture (ISA) defines the instructions executed by Armv8-A compliant processors. The Armv8-A ISA is composed of three instruction sets: A64, A32, and T32. A64 is the 64-bit instruction set executed in the AArch64 execution state, while A32 and T32 are 32-bit instruction sets executed in the AArch32 execution state, with T32 being the Thumb-encoded variant ^[1].

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A64 instruction set ← part of 100% 1e

A64 is one of the three instruction sets that make up the Armv8-A ISA.

A32 instruction set ← part of 100% 1e

A32 is one of the three instruction sets that make up the Armv8-A ISA.

T32 instruction set ← part of 100% 1e

T32 is one of the three instruction sets that make up the Armv8-A ISA.

LINKED ENTITIES

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A64 instruction set PART_OF Extracted graph relationship

A32 instruction set PART_OF Extracted graph relationship

T32 instruction set PART_OF Extracted graph relationship

CITATIONS

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[1] The Armv8-A ISA is composed of three instruction sets: A64, A32, and T32. frestr/armshaker

[2] A64 is the 64-bit instruction set executed in the AArch64 execution state, while A32 and T32 are 32-bit instruction sets executed in the AArch32 execution state. frestr/armshaker

[3] armshaker is a processor fuzzer targeting the Armv8-A ISA that detects hidden or undocumented instructions by executing undefined instruction encodings and checking for SIGILL signals. frestr/armshaker

[4] The limited size of the Armv8-A instruction sets (A64, A32, T32) enables exhaustive search of the full instruction space. frestr/armshaker

[5] An axiomatic-style concurrency model for relaxed virtual memory in Armv8-A was developed in collaboration with Arm and integrated with the full Armv8-A ISA semantics, with use cases from the pKVM hypervisor under development by Google. Relaxed virtual memory in Armv8-A (extended version)

[6] Research has been published on undocumented/hidden instructions in Armv8-A hardware (HASP '20). frestr/armshaker