AHB Bus Interface
ConceptAHB (Advanced High-performance Bus) is one of the selectable on-chip bus interface protocols that can be parameterized into a RISC-V core's RTL design, alongside AXI and TileLink Uncached Light (TL-UL). It is listed as a microarchitectural knob within the broader RISC-V parameterization strategy.
First seen 6/21/2026
Last seen 6/21/2026
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Overview
The AHB Bus Interface refers to the Advanced Microcontroller Bus Architecture (AMBA) High-performance Bus protocol, which can be instantiated as the external interconnect for a RISC-V core. In the context of RISC-V RTL design, AHB is treated as one of several interchangeable bus interface options that can be selected via parameterization.
Role in RISC-V RTL Parameterization
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1 connectionsAHB bus interface is one of the selectable bus interface options in the parameterization scheme.
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[1] AHB is listed as one of the selectable bus interface options (alongside AXI and TL-UL) within the microarchitectural knobs of a parameterizable RISC-V RTL design. Inside RISC-V: Navigating the RTL Design & Verification Landscape
[2] Bus interfaces are presented as a class of microarchitectural knob that includes AXI, AHB, and TL-UL, configurable alongside pipeline depth, branch predictor structures, and cache associativity. Inside RISC-V: Navigating the RTL Design & Verification Landscape