TLB
ConceptIn the provided Logic Fuzzer evidence, TLBs are discussed as processor memory/table elements that can be manipulated during RTL verification. The cited work identifies random invalidation of TLB entries, value fuzzing of already invalid entries, and table pre-population or randomization as ways Logic Fuzzer table mutators can diversify microarchitectural state. It also notes that fuzzed branch-prediction behavior can potentially create iTLB page faults on mispredicted paths.
WIKI
Overview
In the cited Logic Fuzzer work, a TLB appears as one of the processor memory/table structures whose entries can be affected by verification-time fuzzing. The paper describes table mutators as Logic Fuzzer mechanisms that mutate RTL memories, and it lists TLB-entry mutation alongside cache-entry mutation as an example use case.
The provided evidence does not define the internal organization of a TLB or explain address-translation semantics. It supports only the role of TLBs and TLB entries as microarchitectural state that can be targeted or perturbed in the Logic Fuzzer verification context.
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