2026-06-20
4 items 153 entities 180 connections
Processed 66 entities and 72 relations.
FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution Aruna Jayasena Sai Suprabhanu Nallapaneni Prabhat Mishra University of Florida Hardware Fuzzing Coverage-Guided Fuzzing Selective Symbolic Execution Random Test Generation Constrained-Random Verification Property Checking Symbolic Execution Differential Fuzz Testing Semi-Formal Verification Formal Verification Coverage Plateau Branch Coverage Toggle Coverage State Space Explosion Hard-to-Activate Regions Control Flow Graph Finite State Machine Register-Transfer Level Fuzzing Corpus Test Vector Input Mutation Assembly Instruction Sequence Hardware Testbench Design Instrumentation Hardware-Program Context Mapping Source-Destination Pair Extraction SMT Solving Plateau Detection AXI-4 Interface SPI Interface Processor Validation Security Vulnerability Detection Doob Martingale Analysis Azuma-Hoeffding Inequality Cycle-Accurate Simulation VEX Intermediate Representation Register Coverage Metric Physical Memory Protection FuSS Framework Verilator angr Z3 SMT Solver EBMC DifuzzRTL TheHuzz HD-Fuzz ChatFuzz PSOFuzz ProcessorFuzz MABFuzz Cascade SurgeFuzz FormalFuzzer HyPFuzz SoCFuzzer PicoSoC UeRVSoC VeeRwolf CVA6 RISC-V Instruction Set Architecture System-on-Chip
A methodology for validation of microprocessors using equivalence checking - Microprocessor Test and Verification: Common Challenges and Solutions, 2003. Proceedings. 4th Inte
source →Processed 40 entities and 54 relations.
A Methodology for Validation of Microprocessors using Equivalence Checking Prabhat Mishra Nikil Dutt ACES Laboratory University of California Irvine Equivalence Checking Golden Reference Model EXPRESSION ADL Architecture Description Language Register Transfer Language Synthesizable HDL Generation Functional Abstraction Technique DLX Architecture Pipelined Processor Validation Logic Cones Compare Point Matching Theorem Proving Model Checking Unpipelining Verification Compositional Model Checking ADL-driven Validation Framework Pipeline Structure Specification Instruction Decoder Data Path Control Logic Synopsys Formality Design Space Exploration ISDL MIMOLA LISA ADL nML Abstract State Machine Hazard Detection Cadence Affirma Mentor FormalPro Verplex Conformal Embedded Systems Systems-on-Chip Hardware Description Language VHDL
Processed 22 entities and 21 relations.
Golden Reference Model DUT Stimulus Generation Scoreboard Layered Testbench Generator Object-Oriented Programming ALU Instruction Register File Flag Register RTL Design SystemVerilog gameboyprocessor executeALUInstruction test_cpumodel Game Boy CPU ADC Instruction ADD Instruction Half Carry Flag Carry Flag Zero Flag Subtract Flag
Processed 25 entities and 33 relations.
GoldenFuzz hardware fuzzing Golden Reference Model ISA-compliant test generation instruction block concatenation feedback-driven fuzzing coverage-guided fuzzing digital twin two-stage fuzzing framework Device Under Test inter- and intra-instruction quality RISC-V RocketChip BOOM CVA6 BA51-H CVSS v3 severity scoring architectural state exploration test case refinement Lichao Wu Mohamadreza Rostami Huimin Li Nikhilesh Singh Ahmad-Reza Sadeghi Technical University of Darmstadt