Overview

The AXI-4 interface (often appearing as axi4 or axi4_lite in hardware descriptions) is a commonly used bus implementation in System-on-Chip (SoC) designs [chunk 4d39ea11]. It connects SoC components such as processors and memory subsystems by coordinating transactions between an AXI-4 master device and an AXI-4 slave device. Because correct operation requires multiple parallel finite state machines (FSMs) to remain synchronized through strict handshakes, AXI-4 interfaces are a canonical example of a hard-to-activate region in modern hardware.

Transaction Protocol and Synchronization

An AXI-4 write transaction is implemented using two parallel FSMs — one for the master and one for the slave — that coordinate through a sequence of handshake signals [chunk 62df28a0, chunk 4d39ea11]:

1. Master IDLE → ADDR: the master transitions from IDLE to ADDR and asserts awvalid to indicate a valid address is being sent.
2. Slave IDLE → ADDR_READY: the slave detects awvalid, transitions to ADDR_READY, and asserts awready.
3. Master ADDR → WRITE: when both awvalid and awready are asserted, the master moves to WRITE and asserts wvalid with the data.
4. Slave ADDR_READY → WR_READY: the slave transitions to WR_READY and asserts wready.
5. Slave WR_READY → RESPOND: with both wvalid and wready high, the slave captures data and moves to RESPOND, asserting bvalid.
6. Master WRITE → RESPOND: the master detects bvalid and asserts bready.
7. DONE → IDLE: both FSMs transition to DONE before returning to IDLE.