Compare Point Matching

Concept

Compare Point Matching is the phase within an equivalence checking methodology in which compare points (logic-cone output boundaries) of a reference (golden) design are mapped to their corresponding compare points in an implementation design. It is performed using either name-based (non-function) or function-based (signature-analysis) matching techniques, with name-based methods preferred for efficiency.

First seen 6/20/2026

Last seen 6/20/2026

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Overview

Compare Point Matching is a step performed during the match phase of an equivalence checking flow used for validating microprocessors and other digital designs. In this step, the equivalence checking tool attempts to map each compare point of a reference (golden) design to its corresponding compare point in the implementation design, so that the two designs can subsequently be checked for logical equivalence at matching boundaries.

A compare point is the output border of a logic cone—a group of logic delimited by registers, ports, or black boxes. For example, in a typical design block the output OUT1 is the compare point of Cone1. After both the reference and implementation versions of the design are read in and segmented into logic cones, compare point matching establishes which cone outputs correspond to one another across the two designs.

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Equivalence Checking ← uses 95% 1e

Equivalence checking employs compare point matching to map reference and implementation design outputs.

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CITATIONS

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[1] Compare point matching occurs in the match phase of equivalence checking, where the tool attempts to match or map compare points from the reference (golden) design to their corresponding compare point within the implementation design. A methodology for validation of microprocessors using equivalence checking - Microprocessor Test and Verification: Common Challenges and Solutions, 2003. Proceedings. 4th International Workshop

[2] A compare point is the output border of a logic cone, which is a group of logic bordered by registers, ports, or black boxes (e.g., OUT1 is the compare point in Cone1). A methodology for validation of microprocessors using equivalence checking - Microprocessor Test and Verification: Common Challenges and Solutions, 2003. Proceedings. 4th International Workshop

[3] Two types of matching techniques are used: non-function (name-based) and function-based (signature analysis). A methodology for validation of microprocessors using equivalence checking - Microprocessor Test and Verification: Common Challenges and Solutions, 2003. Proceedings. 4th International Workshop

[4] For better performance, the majority of the matching should be completed by more efficient name-based methods. A methodology for validation of microprocessors using equivalence checking - Microprocessor Test and Verification: Common Challenges and Solutions, 2003. Proceedings. 4th International Workshop

[5] Design transformations can result in fewer cones being matched by name-based techniques, slowing match performance, and creating compare rules helps but is itself time-consuming. A methodology for validation of microprocessors using equivalence checking - Microprocessor Test and Verification: Common Challenges and Solutions, 2003. Proceedings. 4th International Workshop

[6] If the implementation is drastically different than the reference design, design rules cannot be written and compare points will have to be manually matched for better performance or matched using more costly function-based matching. A methodology for validation of microprocessors using equivalence checking - Microprocessor Test and Verification: Common Challenges and Solutions, 2003. Proceedings. 4th International Workshop

[7] During transformations such as retiming, logic cones can change so significantly that additional setup is required to successfully verify the designs. A methodology for validation of microprocessors using equivalence checking - Microprocessor Test and Verification: Common Challenges and Solutions, 2003. Proceedings. 4th International Workshop