2026-06-19
6 items 274 entities 347 connections
Processed 48 entities and 75 relations.
Processor Verification Symbolic Execution KLEE Co-Simulation Register-Transfer Level (RTL) Instruction Set Simulator (ISS) RISC-V MicroRV32 RISC-V VP Verilator Fuzzing Coverage-Guided Fuzzing Randomized Instruction Stream Generation Model-Based Test Generation Constraint-Based Test Generation Concolic Testing Bounded Model Checking (BMC) Error Injection Symbolic Memory Sliced Symbolic Registers Symbolic Instruction Generation Voter (Mismatch Detection) RISC-V Formal Interface (RVFI) riscv-formal Virtual Prototype (VP) SpinalHDL LLVM Toolchain Symbolic Execution Interface Instruction Stream VexRiscV PicoRV32 Control and Status Registers (CSRs) Execution Controller Niklas Bruns Vladimir Herdt Rolf Drechsler University of Bremen DFKI GmbH Processor Verification using Symbolic Execution: A RISC-V Case-Study Cross-Level Processor Verification Instruction Bus (IBus) Data Bus (DBus) libFuzzer american fuzzy lop (AFL) OSS-Fuzz Processor-Level Input Stimuli Generation Symbolic Values RV32I Instruction Set
Processed 58 entities and 72 relations.
RISC-V Software-Based Self-Test (SBST) Self Test Library (STL) System-Level Test (SLT) Burn-In Test Bounded Model Checking (BMC) SAT-solver-based test generation Evolutionary algorithm-based test generation Functional test constraint derivation Test Specification Stimuli Generation Hard-to-Test Faults Marginal Defects Non-functional Properties Fault Simulation Stuck-at Fault Model Transition Fault Model Fault Injection (FI) Functional Safety Dual-Core Lockstep (DCLS) Error Correction Code (ECC) Worst-Case Execution Time (WCET) Side-Channel Attack (SCA) Design for Testability (DfT) ISA Extension Instruction Set Simulator Formal Specification Chipyard Rocket Chip Generator BOOM (Berkeley Out-of-Order Machine) Ibex CV32E40P (RI5CY) CVA6 (Ariane) VexRiscv PicoRV32 Greybox Test Generation Assembly Program Generation Modular ISA Control and Status Registers (CSRs) Memory Model Incremental Processor Design Functional Test Program Fuzzing for Test Generation SoC Generation Framework Register Initialization Sequence Fault Propagation Path Stress Program Pipelined Processor A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors Politecnico di Torino University of Freiburg University of Stuttgart Leiden University Universitat Politècnica de València Advantest Europe RTL FPGA-based Fault Injection Simulation-based Fault Injection
Processed 20 entities and 25 relations.
GoldenFuzz Hardware Fuzzing Golden Reference Model Device Under Test ISA-compliant Test Generation Instruction Block Concatenation Feedback-driven Coverage Mechanism Coverage-guided Fuzzing Digital Twin Architectural State Exploration Vulnerability Discovery RISC-V RocketChip BOOM CVA6 BA51-H CVSS v3 GoldenFuzz: Generative Golden Reference Hardware Fuzzing Test Case Refinement Two-stage Fuzzing Framework
Processed 76 entities and 85 relations.
Fuzz Testing Hardware Fuzzing RTL Fuzzing FPGA-Accelerated Fuzzing Software Fuzzing Coverage-Guided Fuzzing Generation-Based Fuzzing Mutation-Based Fuzzing Grey-Box Fuzzing Black-Box Fuzzing White-Box Fuzzing Differential Testing Directed Fuzzing Mux Coverage Instrumentation Register Coverage CSR Transition Coverage Branch Coverage Formal Verification Dynamic Verification Static Verification Seed Trimming Bit-Flipping Mutation Arithmetic Mutation Block-Based Mutation Dictionary-Based Mutation Linear-Feedback Shift Register (LFSR) True Random Number Generator (TRNG) AFL++ RFuzz DirectFuzz DiFuzzRTL TurboFuzz ProcessorFuzz Profuzz Verilator Wireshark Libero SoC Design Suite verilog-ethernet IPv4 RTL FPGA Device Under Test (DUT) ISA Simulation Finite State Machine (FSM) Control and Status Registers (CSRs) Test Throughput Code Coverage Input Grammar System on Chip (SoC) Lookup Table (LUT) Ethernet Frame Header Checksum Seed Input Bug Oracle FIFO Queue Alexander Lindskog Filip Ripstrand Petter Källström Kent Palmkvist Axel Stafström Michal Zalewski Linköping University Sectra Google Microchip Arrow Efinix RFuzz Paper AFL White-Paper DiFuzzRTL Paper ProcessorFuzz Paper TurboFuzz Paper Profuzz Paper Hardware Fuzzer (On-Chip) Software Fuzzer (Host-Based) Direct Memory Access (DMA)
Processed 39 entities and 49 relations.
Fuzzing ProcessorFuzz SIGFuzz Control and Status Registers (CSR) CSR Transition Coverage Coverage Feedback Microarchitectural Timing Side Channels RTL Simulation ISA Simulation Mutation Engine Seed Corpus Assembly Test Programs Golden Model Trace Comparison Cycle-Accurate Commit Trace Signature Extraction Spectre-Style Attack Hardware Description Language (HDL) Rocket Processor BOOM Processor BlackParrot Processor Dromajo ISA Simulator DifuzzRTL RISC-V ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance SIGFuzz: A Framework for Discovering Microarchitectural Timing Side Channels Chathura Rajapaksha Sadullah Canakci Leila Delshadtehrani Anoop Nataraja Michael Bedford Taylor Manuel Egele Ajay Joshi Boston University University of Washington OSS-Fuzz American Fuzzy Lop (AFL) RFuzz DirectFuzz
Processed 33 entities and 41 relations.
Genesys Pseudo-Random Test-Program Generation Functional Verification Methodology Verification Plan Testing Knowledge Periodic Regression Set Coverage Subsets Full-Load Testing Random Testing Corner Case Testing Bug-Driven Activity Model-Based Test Generation Directives File Generation-Simulation Cycle Hardware Testing Behavioral Simulation Architecture Specification Model Commercial Test Suites Escape Bugs Floating Point Unit Verification Genesys-x86 Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator Laurent Fournier Yaron Arbetman Moshe Levinger IBM Haifa Research Lab x86 Architecture Pentium FDIV Bug Pentium FIST Bug Bit Sequence Pattern Testing Constraint-Based Test Generation PowerPC Processor Verification VLIW Architecture