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2026-06-18

4 items 115 entities 138 connections

COREV-DV — CORE-V Verification Strategy documentation

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Processed 14 entities and 13 relations.

COREV-DV riscv-dv core-v-verif instruction stream generator UVM SystemVerilog RISC-V uvm_object corev_asm_program_gen.sv riscv_gen_program_header::gen_program_header() board support package CV32E40P Google OpenHW Group

Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation

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Processed 52 entities and 60 relations.

Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation Miroslav N. Velev Randal E. Bryant Carnegie Mellon University Memory Shadowing Symbolic Ternary Simulation Correspondence Checking Burch and Dill Pipeline Verification Method Efficient Memory Model (EMM) Ternary Simulation Symbolic Trajectory Evaluation (STE) Pipeline Verification Commutative Diagram Correctness Criterion Abstraction Function Uninterpreted Functions with Equality Symbolic Binary Simulation Address Set Expression (ASExpr) Data Set Expression (DSExpr) Control Expression (CExpr) Universal Data Set (UD) Ordered Binary Decision Diagrams (OBDDs) Write Operation (EMM) Read Operation (EMM) ShadowRead Operation CompareForContainment Function GenDataExpr Function Variable-Group Indexing VerifyGenerality Procedure MIPS Pipeline Shortened Pipelined MIPS (SPMIPS) Instruction Set Architecture (ISA) Pipeline Flushing Forwarding Logic Verification Superscalar Processor Verification Sawada Hunt Burch Dill Jones Seger Windley Pandey Symbolic Model Checking Register-Transfer Level (RTL) Transistor-Level Verification Approximate Union Operation Conservative Approximation Ternary Correspondence Checking NOP Instruction Instruction Memory (IMem) Register File Program Counter (PC)

An Efficient and Uniform CSP Solution Generator Generator

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Processed 6 entities and 4 relations.

uniform sampling constraint satisfaction problem (CSP) rejection sampling constraint-based sampling constraint-based generator solution uniformity

StimulusRL: A Universal Deep Reinforcement Learning Stimulus Agent for Coverage-Driven Chip Design Verification

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Processed 43 entities and 61 relations.

StimulusRL DVSBench Deep Q-Network deep reinforcement learning coverage-driven generation constrained-random verification coverage-guided mutation fuzzing differential testing Markov decision process functional coverage closure cocotb Verilator UVM RTL UCIS DifuzzRTL BugsBunny AFL++ GraphCov FIFO8 ALU32 DMCache RRArb4 SPIM8 epsilon-greedy exploration experience replay temporal-difference learning reward shaping legality masking Bayesian network stimulus generation SystemVerilog coverage-guided fuzzing curriculum learning Adam optimizer Jingyi Chen Chenyao Zhu Carnegie Mellon University UC Berkeley StimulusRL: A Universal Deep Reinforcement Learning Stimulus Agent for Coverage-Driven Chip Design Verification design verification coverage area-under-curve Python DV evaluation harness hierarchical action modeling