2026-06-17
2 items 76 entities 74 connections
Processed 23 entities and 21 relations.
UVM Simulation-based Verification Environment RISC-V DV Random Instruction Generator RTL Simulation Compiled Instruction Binaries Memory Model Instruction Fetch Interface Load-Store Unit Interface Interrupt Interface Agent Interrupt Stimulus Generation Debug Stimulus Generation Slave Sequence Instruction Set Simulator Golden Model Trace Log Comparison Coverage-driven Verification Tests and Sequence Library core_ibex_base_test Riviera-PRO Ibex Core RISC-V Google Aldec
Processed 53 entities and 53 relations.
Verification of a RISC-V system with multiple cores Oscar Palomar Roberto Ignacio Genovese Iván Díaz Ortega Albert Aguilera Abdul Rauf Barcelona Supercomputing Center ARM RISC-V UVM Spike ISS riscv-dv riscv-tests random binary generation directed tests co-simulation reference model functional coverage cache hierarchy out-of-order core Core-UVM environment CPU-Subsystem UVM environment RTL SystemVerilog DPI SVA assertions interrupt generation AXI interface scoreboard instruction set simulator RISC-V compliance tests RVV 1.0.0 vector instructions atomic instructions stress tests vector memory instructions register randomization AXI Master VIP Sargantana Lagarto KA Lagarto OX Barcelona Zettascale Lab JTAG interface verification DMA interface verification exception and trap handlers bootrom preloading regression testing Core-UVM environment CPU-Subsystem UVM environment Spike ISS riscv-dv riscv-tests Sargantana Lagarto KA Lagarto OX Barcelona Supercomputing Center