Direct Memory Access (DMA)

Concept

Direct Memory Access (DMA) is a data-movement mechanism that allows peripheral devices and accelerators to transfer data to and from memory without continuous CPU involvement. In modern compute contexts it underpins high-bandwidth host-accelerator transfers (e.g., in AXI4MLIR/accel), enables in-SRAM cryptographic kernels on MCUs, and is leveraged by FPGA-accelerated hardware fuzzers such as RFuzz to exchange test cases and results between a fuzzer, shared memory buffers, and a synthesized design-under-test.

First seen 6/16/2026

Last seen 6/19/2026

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Direct Memory Access (DMA)

Definition

Direct Memory Access (DMA) is a hardware mechanism that permits data transfer between memory and a peripheral, accelerator, or other functional block without requiring the CPU to handle each data element. By offloading bulk transfers, DMA frees the processor to perform other work and typically provides much higher throughput for moving large data streams.

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RFUZZ ← uses 95% 1e

RFuzz uses DMA to communicate between the fuzzer and the synthesized DUT on FPGA.

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CITATIONS

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[1] RFuzz uses a high-bandwidth direct memory access channel to transfer test cases and results between the fuzzer/shared memory and the synthesized DUT on a CPU+FPGA SoC. Fuzzing IPv4 modules on FPGAs

[2] In AXI4MLIR, data is copied from heap-allocated buffers into contiguous DMA-mapped buffers as a redundant staging operation; zero-copy data movement reduces main-memory data movement by up to 2×. Defeat the Heap: Zero-Copy Data Movement in AXI4MLIR

[3] CryptoSRAM leverages the fact that MCUs use physical addressing and DMA to manage SRAM, enabling seamless integration of in-SRAM cryptographic compute with minimal hardware overhead. CryptoSRAM: Enabling High-Throughput Cryptography on MCUs via In-SRAM Computing

[4] Data-flow-based post-silicon coverage metrics treat DMA transfers (e.g., memory to USB peripheral) as canonical on-chip data flows whose measurement quantifies validation effectiveness. Unified Coverage Methodology for SoC Post-Silicon Validation