2026-06-22
4 items 135 entities 165 connections
Processed 53 entities and 54 relations.
EPEX Equivalent Program Execution Processor Verification Test Program Generation Equivalence Checking ISA-level Verification Architectural State Formal ISA Model RTL Instruction Set Architecture Instruction Set Simulator Constrained Random Test Generation Simulation-Based Verification Formal Verification Satisfiability Modulo Theories Program Synthesis Bounded Model Checking Symbolic Quick Error Detection Quick Error Detection Coverage-Guided Fuzzing Mutation Testing Control Path Variation Instruction Replacement Effect Constraint Chain Constraint Z3 SMT Solver CBMC riscv-formal OneSpin 360 DV RISC-V DV RISC-V Torture Test Generator VexRiscv SpinalHDL MicroTESK Genesys-Pro SMT-lib v2.0 Universal Verification Methodology RISC-V ISA Cross-Level Testing Compliance Test Suite Dhrystone Benchmark Instruction Sequence Equivalence EPEX: Processor Verification by Equivalent Program Execution Lucas Klemmer Daniel Große Johannes Kepler University Linz RISC-V Foundation Barrel Shifter Pipeline Stage Theorem Proving Bayesian Network Test Generation RISC-V Sail Model epex-formal-rv32-model
Corner Case Scenario Generation (CCSG) Tool: A Novel Approach to find corner case bugs in next generation SoCs
source →Processed 21 entities and 30 relations.
Corner Case Scenario Generation Tool CCSG Corner Case Scenario Generation SoC Pre-Silicon Verification Mode Transition Verification Asynchronous Event Injection Multi-Power Domain Verification Multi-Mode Operation External Reset External Interrupt External Wakeup Clock Failure Precision Event Sweeping Post-Processing of Simulation Results Randomization of Asynchronous Events SoC Mode Control Module CCSG Verilog Implementation Low Power Mode Naveen Jakhar Department of Telecommunications, Government of India
Processed 47 entities and 67 relations.
MicroTESK Test Program Generation Random Generation Combinatorial Generation Template-Based Generation Model-Based Generation Constraint-Based Random Generation RAVEN Genesys-Pro Instruction-Level Model Microarchitectural Model Architecture Description Language Sim-nML Test Template Test Situation Coverage Model Design Model Self-Checking Test Test Oracle SMT Solver Yices Z3 SMT-LIB Java Constraint Solver API Fault Model Operation State Machine Extended Finite State Machine Pipeline Model EXPRESSION ADL SMV Test Sequence Generator Test Data Generator Microprocessor Verification Instruction Set Architecture Memory Management ISPRAS IBM Research Obsidian Software Alexander Kamkin Tatiana Sergeeva Andrei Tatarnikov Artemiy Utekhin Test Template Processor Constraint Solver Engine MIPS Instruction Set Test Program Composition MicroTESK: An Extendable Framework for Test Program Generation