Barrel Shifter

Concept

A barrel shifter is a combinational digital circuit that can shift or rotate a data word by any number of bit positions in a single operation, implemented as a permutation network built from successive layers of multiplexers (and, in some designs, transmission gates). Evidence describes its use as a building block in CORDIC/normalized SVD hardware and as the structural basis of a Physical Unclonable Function (PUF) that exploits per-path delay variation. A related processor-design case study shows how barrel-shift logic can be decomposed into reverse/right-shift/reverse stages on a RISC-V core.

First seen 6/22/2026

Last seen 6/22/2026

Evidence 1 chunks

Wiki v1

WIKI

Barrel Shifter

Overview

A barrel shifter is a combinational digital circuit that performs an arbitrary-direction, arbitrary-amount shift (or rotation) of a data word within a single clock cycle, without iterating over a shift count. It is commonly realized as a permutation network—layers of multiplexers (or transmission gates) that route each input bit to a chosen output position based on the shift amount.

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

CITATIONS

5 sources

5 citations — click to expand

[1] A barrel shifter is used as a primitive permutation network for a Physical Unclonable Function that captures per-path delay variation. Barrel Shifter Physical Unclonable Function Based Encryption

[2] The BS-PUF was implemented using transmission gates in an 8-level common-centroid layout in 0.13 µm technology, and post-layout simulations passed selected NIST randomness tests, showed stability comparable to Ring Oscillator PUFs, and resisted logistic-regression modeling with 100,000 plaintext–ciphertext pairs. Barrel Shifter Physical Unclonable Function Based Encryption

[3] Barrel shifters (B-shifters) are listed among the basic combinational modules—alongside adders, multiplexers, encoders, and comparators—used in a normalized SVD architecture based on Givens fast rotations. The Normalized Singular Value Decomposition of Non-Symmetric Matrices Using Givens fast Rotations

[4] In the normalized SVD systolic design, the diagonal processor uses priority encoders, barrel shifters, and comparators to calculate rotation angles, while both processors apply the angles through adders. The Normalized Singular Value Decomposition of Non-Symmetric Matrices Using Givens fast Rotations

[5] A barrel shifter was integrated into a VexRiscv RISC-V core by decomposing left shifts into reverse, variable right-shift, and reverse-output stages, with a configurable location of the final reverse operation in the execute or memory pipeline stage. EPEX: Processor Verification by Equivalent Program Execution