Clock Failure
ConceptClock failure refers to the abnormal condition in which a clock signal ceases to propagate correctly through clock-distribution or clock-generation circuitry, causing downstream logic to lose its timing reference. In digital phase-locked and delay-locked loops, clock failure can be triggered by excessive bias steps during locking, while in complex SoC power-management verification, it is treated as one of the asynchronous events that can occur during mode transitions and is targeted by corner-case scenario generation tools.
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Clock Failure
Definition
A clock failure is an abnormal condition in which a clock signal fails to propagate correctly through a clock-generating or clock-distributing structure, depriving downstream sequential logic of a valid timing reference. The term is used in two related but distinct contexts in the evidence base: (1) the hardware context of phase-/delay-locked loops, where large step sizes during locking can stall clock propagation through a voltage-controlled delay line (VCDL), and (2) the SoC power-management verification context, where a clock failure is enumerated as one of several asynchronous events (alongside external resets, interrupts, and wakeups) that may coincide with an ongoing mode transition.
Clock Failure in Delay-Locked Loops
In mixed-mode delay-locked loops (MM-DLLs), the locking process relies on adjusting a voltage-controlled delay line (VCDL) until the delay matches a target value. When a binary search (BS) locking scheme is used, the controller applies large voltage steps at the start of locking to converge quickly. These large steps can introduce significant bias overshoots, which in turn can produce a clock failure condition, defined as the state in which "clocks fail to propagate through the VCDL." Without mitigation, such a failure stalls the locking process.
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