Clock Failure
Definition
A clock failure is an abnormal condition in which a clock signal fails to propagate correctly through a clock-generating or clock-distributing structure, depriving downstream sequential logic of a valid timing reference. The term is used in two related but distinct contexts in the evidence base: (1) the hardware context of phase-/delay-locked loops, where large step sizes during locking can stall clock propagation through a voltage-controlled delay line (VCDL), and (2) the SoC power-management verification context, where a clock failure is enumerated as one of several asynchronous events (alongside external resets, interrupts, and wakeups) that may coincide with an ongoing mode transition.
Clock Failure in Delay-Locked Loops
In mixed-mode delay-locked loops (MM-DLLs), the locking process relies on adjusting a voltage-controlled delay line (VCDL) until the delay matches a target value. When a binary search (BS) locking scheme is used, the controller applies large voltage steps at the start of locking to converge quickly. These large steps can introduce significant bias overshoots, which in turn can produce a clock failure condition, defined as the state in which "clocks fail to propagate through the VCDL." Without mitigation, such a failure stalls the locking process.
To recover from this condition, a toggle detector is added that monitors clock activity at the VCDL output:
- Upon detecting that the clock has stalled (i.e., a clock failure is present), the toggle detector signals the binary search controller.
- The controller then reverts the DAC code to the previous working code that had yielded a propagating clock.
- The binary search is resumed with a reduced step size, preventing the bias overshoot that caused the failure.
This technique enables the MM-DLL to lock across a broad frequency range (533 MHz to 4.26 GHz in the cited 3-nm FinFET implementation) while avoiding the clock-failure corner of the locking search space.
Clock Failure as an Asynchronous Event in SoC Mode Transitions
In pre-silicon verification of complex SoCs that support multiple power domains and operating modes, clock failure is one of the asynchronous events that can occur during the window of an ongoing mode transition. The other events in this category are external resets, external interrupts, and external wakeups. The combination of such events with mode transitions introduces entropy that conventional verification— including naive randomization of asynchronous events—fails to cover exhaustively, because events aligned to a particular clock edge inside a transition window can be missed entirely.
To close this coverage gap, corner-case scenario generation (CCSG) tools accept clock failure (among other event types) as a user-selected event category. The tool then sweeps that event with high temporal precision across the edges of a local clock that is asynchronous to the testbench and to system clocks, ensuring that every clock-edge-aligned position within the mode-transition window is exercised. After the sweep, intelligent post-processing aggregates occurrences into counts of successful versus failed mode transitions so that verification engineers can identify clock-failure-induced corner-case bugs that would otherwise escape pre-silicon verification and surface only in customer use cases.
Related Concepts
- CCSG (Corner Case Scenario Generation Tool) — A Verilog-coded verification utility that sweeps asynchronous events, including clock failure, across the edges of an asynchronous local clock to expose corner-case mode-transition bugs.
- Asynchronous Event Injection — The general technique of injecting events such as clock failures into specific windows of an ongoing operation; clock failure is one type of event that can be injected.