capability pointer

Concept

A capability pointer is an unforgeable, tagged pointer used in the CHERI architecture that extends an integer memory address with metadata such as bounds, permissions, and object type information. Capability pointers replace traditional integer pointers in CHERI programs, enabling hardware-enforced spatial memory safety and fine-grained protection, and form the substrate for related concepts such as capability bounds and capability permissions.

First seen 6/21/2026

Last seen 6/21/2026

Evidence 2 chunks

Wiki v1

WIKI

Capability Pointer

A capability pointer is the fundamental architectural primitive of the CHERI (Capability Hardware Enhanced RISC Instructions) instruction-set extension. It replaces traditional integer memory pointers in compiled programs and is augmented with metadata and a validity tag so that the hardware can enforce how the pointer may be dereferenced.

Definition and Role in CHERI

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NEIGHBORHOOD

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RELATIONSHIPS

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CHERI ← uses 100% 2e

CHERI uses capability pointers to replace traditional integer memory addresses.

capability bounds extends → 90% 1e

Capability pointers include bounds as part of their metadata.

capability permissions extends → 90% 1e

Capability pointers include permissions as part of their metadata.

LINKED ENTITIES

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CHERI USES Extracted graph relationship

capability bounds EXTENDS Extracted graph relationship

capability permissions EXTENDS Extracted graph relationship

CITATIONS

9 sources

9 citations — click to expand

[1] Capabilities are an architectural primitive that compilers, systems software, and applications use to constrain their own future execution, and traditional pointers in programs are replaced by capabilities. A RISC-V CHERI VP: Enabling System-Level Evaluation of the Capability-Based CHERI Architecture

[2] Capabilities extend integer memory addresses (now 128 bit) and carry metadata (bounds, permissions, etc.) that controls how the capability may be used. A RISC-V CHERI VP: Enabling System-Level Evaluation of the Capability-Based CHERI Architecture

[3] General-purpose registers become 129 bits wide (64-bit address + 64-bit metadata + 1-bit validity tag), the program counter is extended with a capability, and tagged memory protects capability-sized and -aligned words in DRAM with an out-of-band validity tag transported over an extended bus architecture. A RISC-V CHERI VP: Enabling System-Level Evaluation of the Capability-Based CHERI Architecture

[4] Capability metadata includes bounds (compressed encoding of base and top), permissions (Load, Store, Execute, etc.), an object type field supporting object-method validation, and reserved fields. A RISC-V CHERI VP: Enabling System-Level Evaluation of the Capability-Based CHERI Architecture

[5] Tags are stored out-of-band from normal data, are atomically bound to capabilities, and validate capability integrity and derivation in registers and memory. A RISC-V CHERI VP: Enabling System-Level Evaluation of the Capability-Based CHERI Architecture

[6] In Hybrid-Mode, the capability-mode flag (flag_cap_mode) is required so that CHERI-aware and legacy code can run side by side. A RISC-V CHERI VP: Enabling System-Level Evaluation of the Capability-Based CHERI Architecture

[7] A CHERI execution of an out-of-bounds array read raises a LengthViolation exception, demonstrating hardware-enforced spatial memory safety. A RISC-V CHERI VP: Enabling System-Level Evaluation of the Capability-Based CHERI Architecture

[8] CHERI is a hardware-based approach developed by the University of Cambridge beginning in 2010 to increase memory safety of RISC processors, with variants for RISC-V, MIPS, ARM (Morello), and x86. A RISC-V CHERI VP: Enabling System-Level Evaluation of the Capability-Based CHERI Architecture

[9] CHERI-D associates object identification metadata with capability pointers to provide temporal integrity of allocations on top of CHERI's spatial safety. CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety