2026-07-18
5 items 243 entities 291 connections
Processed 43 entities and 42 relations.
RISC-V ISA scope RISC-V profiles custom instructions random instruction generation constrained-random stimulus generation functional coverage coverage model lockstep co-simulation reference model formal verification directed tests architectural certification tests instruction retirement comparison debug visibility trace infrastructure privilege modes CSR interactions exception handling interrupt handling SoC integration verification software-facing verification coverage closure verification plan RTL UVM pipeline hazards PMP protection features debug mode riscv-dv Sail RISC-V model RISCOF riscv-arch-test riscv-formal RISC-V International OpenHW Group CHIPS Alliance YosysHQ Alpinum Consulting RISC-V Instruction Set Manual Volume I RISC-V Debug Specification CORE-V Verification Strategy CORE-V
A Comparison of Three Verification Techniques: Directed Testing, Pseudo-Random Testing and Property Checking
source →Processed 42 entities and 48 relations.
A Comparison of Three Verification Techniques: Directed Testing, Pseudo-Random Testing and Property Checking Mike G. Bartley Darren Galpin Tim Blackmore Elixent Ltd Infineon Technologies UK Ltd Directed Testing Pseudo-Random Testing Property Checking Specman Elite GateProp Bus Functional Model (BFM) e Language Verification Component (eVC) Design Under Test (DUT) LFI Bus Bridge LFI-IBC32 LFI-S Local Memory Bus (LMB) Flexible Peripheral Interface Bus (FPI) Functional Coverage Structural Coverage FSM Transition Coverage Protocol Checker Formal Verification Constraint-Driven Testing Transaction Coverage Bus Protocol Properties Transaction Properties Toggle Coverage State Space Explosion Verification IP Reuse Semi-Formal Verification 0-In Search Verisity Accellera Siemens Register-Transfer Level (RTL) VHDL Black Box Test Specification White Box Testing Bug Curve Advanced High-performance Bus (AHB)
Processed 55 entities and 60 relations.
PORTRUSH Write Port Contention Write Request Graph Hierarchical Aggregation and Decoding Contention-guided Hardware Fuzzing Hardware Fuzzing Transient Execution Attack Side-Channel Attack Speculative Execution Register-Transfer Level BOOM NutShell Rocket Core RISC-V Particle Swarm Optimization Differential Testing Assertion-Based Verification Seed Corpus Register Coverage Write Request Behavior Coverage Signal Decoder Signal Aggregation Engine Out-of-Order Execution Cache Side-Channel Attack FLUSH+RELOAD PRIME+PROBE Evict+Time SMoTherSpectre Spectre-STC MSHRush Birgus-variant FIRRTL Compiler SpecDoctor Reorder Buffer Miss Status Holding Register Register File Priority Arbitration Formal Verification Multiplexer Instruction Sequence Mutation Seed Minimization National University of Defense Technology Peihong Lin Pengfei Wang Lei Zhou Gen Zhang Xu Zhou Wei Xie Zhiyuan Jiang Kai Lu Design Under Test Kernel Page-Table Isolation Chisel Depth-First Search Binary Search Seed Minimization
Processed 57 entities and 86 relations.
SiliFuzz Fuzzing Coverage-Guided Mutation-Based Fuzzing Generation-Based Fuzzing Blackbox Fuzzing Greybox Fuzzing Structure-Aware Fuzzing Differential Testing Proxy-Based Fuzzing Corpus Distillation Snapshot-Based Testing Nondeterminism Elimination Register Scrambling Cross-Pollination of Corpora libFuzzer AFL Honggfuzz Syzkaller XED Unicorn ifuzz Sandsifter UISFuzz gem5 Simics SiliFuzz Checker Silent Data Corruption CPU Logic Bug CPU Electrical Defect Code Coverage Snapshot Fuzzing Corpus Instruction Sequence Generation x86_64 Instruction Encoding Fuzzing Dictionary Snapshot Player RTL Design CPU Emulator as Proxy Microarchitectural State Quarantine Pool End State Recording Feedback Loop F2XM1 Defect Illegal Instruction Overshoot Defect FCOS Miscomputation Defect Missing x87 Data Pointer Update Defect SiliFuzz: Fuzzing CPUs by Proxy Kostya Serebryany Maxim Lifantsev Konstantin Shtoyk Doug Kwan Peter Hochschild Google LLVMFuzzerTestOneInput XED Integration Unicorn fuzz_emu_x86_64.c Corpus Distillation Register Scrambling
Processed 46 entities and 55 relations.
RISCV-DV SystemVerilog UVM RISC-V RTL RV32IMAFDC RV64IMAFDC CSR privileged mode page table randomization trap and interrupt handling MMU stress test illegal instruction generation HINT instruction generation random branch instruction generation debug mode support instruction generation coverage model co-simulation spike riscv-ovpsim sail-riscv Synopsys VCS Cadence Incisive/Xcelium Mentor Questa riscv-gcc run.py gen_csr_test.py riscv_instr_gen_config.sv riscv_core_setting.sv riscv_instr_cover_group.sv riscv_load_store_instr_lib.sv cov.py directed instruction stream random instruction generation functional coverage handshaking mechanism PMP virtual address translation memory region configuration regression test Google LowRISC IBEX RISC-V core ISS simulation sub-program generation CSR test generation