Bug Curve

Concept

A bug curve is a plot of the cumulative number of bugs found in a design under test (DUT) over time, used to track verification progress. In hardware verification projects it is typically expected to follow an S-shape: a slow start while the test bench is constructed and debugged, a steep rise as testing of the DUT begins and new areas are exercised (often also uncovering test bench bugs), and finally a flattening out as the test bench and DUT reach maturity.

First seen 7/18/2026

Last seen 7/18/2026

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Bug Curve

Definition

A bug curve is a plot of the cumulative number of bugs discovered in a design under test (DUT) against time (or verification effort). It is used as a project-management and sign-off artefact during hardware functional verification.

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A Comparison of Three Verification Techniques: Directed Testing, Pseudo-Random Testing and Property Checking ← mentions 100% 2e

The paper discusses bug curves as a way to measure design maturity.

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A Comparison of Three Verification Techniques: Directed Testing, Pseudo-Random Testing and Property Checking MENTIONS Extracted graph relationship

CITATIONS

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[1] Bug find rates are often expected to follow an S-curve shape: the number of bugs found rapidly increases as verification effort is increased, and gradually reduces as the DUT reaches maturity. A Comparison of Three Verification Techniques: Directed Testing, Pseudo-Random Testing and Property Checking

[2] If the levelling out in the bug curve is not seen, it can be an indication that more time is needed to debug the design. A Comparison of Three Verification Techniques: Directed Testing, Pseudo-Random Testing and Property Checking

[3] A cumulative total flattening out completely for a sufficient time can be used as a sign-off criterion, as it suggests that maturity has been reached. A Comparison of Three Verification Techniques: Directed Testing, Pseudo-Random Testing and Property Checking

[4] Bugs were recorded using an issue tracking system that allowed statistics to be gathered such as the cumulative number of bugs found, the number fixed, and whether they occurred in the design or test bench. A Comparison of Three Verification Techniques: Directed Testing, Pseudo-Random Testing and Property Checking

[5] Figure 2 (LFI-S Bug Curves) shows the bug curve seen during the LFI-S project and clearly shows the progression of the project through its life cycle: test bench construction/debug, rapid upward movement as DUT testing begins, continued increases as new DUT functionality and verification IP areas are tested, and flattening as the test bench and DUT reach maturity. A Comparison of Three Verification Techniques: Directed Testing, Pseudo-Random Testing and Property Checking