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Advanced High-performance Bus (AHB)

Concept

The Advanced High-performance Bus (AHB) is a high-speed on-chip bus used in System-on-Chip (SoC) designs, typically connecting processors and memory. It supports complex transactions such as burst transfers, which require bridging to simpler, single-cycle protocols like the Advanced Peripheral Bus (APB). AHB-based designs are widely used as targets for functional verification, including property checking of bus protocols.

First seen 7/18/2026
Last seen 7/18/2026
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Advanced High-performance Bus (AHB)

The Advanced High-performance Bus (AHB) is a high-performance on-chip interconnect used in System-on-Chip (SoC) architectures. It is designed for high-speed operations and is typically employed to connect processors and memory subsystems.

Role in SoC Architectures

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RELATIONSHIPS

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A Comparison of Three Verification Techniques: Directed Testing, Pseudo-Random Testing and Property Checking ← mentions 100% 1e
The paper mentions plans to develop bus protocol packages for AHB.

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A Comparison of Three Verification Techniques: Directed Testing, Pseudo-Random Testing and Property Checking MENTIONS Extracted graph relationship

CITATIONS

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3 citations — click to collapse
[1] AHB is a high-speed on-chip bus used in SoC designs for connecting processors and memory, and operates alongside lower-speed buses such as APB. Integrated AHB to APB Bridge Using Raspberry Pi and Artix-7 FPGA
[2] AHB supports burst transfers, while APB uses a non-pipelined, single-cycle protocol, requiring bridge logic for clock synchronization, transaction conversion, and flow control. Integrated AHB to APB Bridge Using Raspberry Pi and Artix-7 FPGA
[3] Bus protocol constraints and properties are highly reusable across verification modules, and standardized protocols such as AHB are candidates for reusable verification packages that standardize signal names. A Comparison of Three Verification Techniques: Directed Testing, Pseudo-Random Testing and Property Checking