2026-07-19
6 items 197 entities 218 connections
Processed 6 entities and 4 relations.
Processed 10 entities and 11 relations.
Processed 52 entities and 55 relations.
Fuzzing Coverage-Guided Fuzzing Firmware Fuzzing MMIO Modeling Emulation-Based Fuzzing Crash Bucket Analysis Crash Trace Replay Fault Injection Voltage Glitching Debug Mode MMIO Injection Static MMIO Read Patching Delay Function Patching Reverse Engineering Proof-of-Concept Exploit Development Fuzzware QEMU Unicorn Engine Ghidra nrfjprog Aurora-Fuzz Aurora-Fuzz Configuration Script Memory-Mapped I/O (MMIO) Instruction Pointer Link Register Stack Pointer UICR FICR Coverage Feedback Translation Blocks Remote Code Execution Denial of Service Stack Overflow Raw Input ISA Emulator Interrupt DMA Fuzzware: Using Precise MMIO Modeling for Effective Firmware Fuzzing Tobias Scharnowski Nils Bars Moritz Schloegel Eric Gustafson Marius Muench Giovanni Vigna Christopher Kruegel Thorsten Holz Ali Abbasi Noah Holmdin Ravishankar Borgaonkar SINTEF NTNU Nordic Semiconductor nRF52840 Development Kit
Processed 37 entities and 51 relations.
FP-RVVTS RVVTS RISCV-DV Spike Spike FF RISC-V VP++ QEMU SoftFloat FloppyFloat riscvOVPsim context-free grammar specification single-instruction isolation dependency annotation constrained-random instruction generation negative testing positive testing functional coverage measurement failure cause analysis RISC-V FP extensions IEEE 754 floating-point arithmetic instruction set architecture RISC-V Instruction Sequence Generator rounding mode NaN handling Float Fight: Verifying Floating-Point Behavior in RISC-V Simulators Single instruction isolation for RISC-V vector test failures FloppyFloat: An open source floating point library for instruction set simulators RISC-V VP++: Next generation open-source virtual prototype Katharina Ruep Manfred Schlägl Daniel Große Johannes Kepler University Linz UC Berkeley RISC-V International Google
Processed 57 entities and 62 relations.
Single Instruction Isolation for RISC-V Vector Test Failures Manfred Schlägl Daniel Große Johannes Kepler University RISC-V RISC-V Vector Extension (RVV) RVVTS Single Instruction Isolation with Code Minimization RISC-V VP++ QEMU Instruction Sequence Generator (ISG) RISCV-DV Google FORCE-RISCV OpenHW Group positive testing negative testing Device Under Test (DUT) functional coverage coverage-guided test generation constraint solving for test generation grammar-based ISG Machine State Code Fragment Code Block CodeErrMinRunner CovGuidedTestsetGenerator CodeCompareRunner TestsetCodeErrMinRunner RefCovRunner GDBRunner CodeCheckRunner Spike riscvOVPsim Imperas Delta Code Reduction (Binary Search) Valid Sequences (VS) test set Invalid+Valid Sequences (IVS) test set Merged Sequences (MS) test set Execution Runner Symbolic Quick Error Detection (SQED) Bounded Model Checking (BMC) coverage-guided fuzzing Universal Verification Methodology (UVM) RTL SIMD RISC-V Sail specification model Program Counter (PC) Control and Status Register (CSR) GDB Remote Debug Protocol (RDB) Executable and Linkable Format (ELF) RISC-V compliance test suite EPEX Jupyter notebooks Instruction Set Simulator (ISS) Virtual Prototype (VP) bounded load/store operations
Processed 35 entities and 35 relations.
TestRIG RVFI-DII QuickCheckVEngine QuickCheck Sail RISC-V CHERI tandem verification mutation coverage code coverage randomised testing random instruction generation RVFI trace golden model executable simulator test shrinking microarchitectural mutation coverage RTL SQLite Sail JAL semantics Toooba CVA6 Microsoft Research lowRISC SCI Semiconductor University of Cambridge SRI International Peter Rugg Alexandre Joannou Jonathan Woodruff Franz A. Fuchs Simon W. Moore DII (Direct Instruction Injection) hardware capabilities memory safety