This course introduces participants to best-practice CPU Design Verification (DV) strategies to help them contribute effectively to real projects (see the objectives). It is aimed at engineers new to CPUs and/or CPU verification, including those who are verifying CPU integration into an SoC (System-on-Chip) or who want to better understand it (target audience). It is delivered entirely online, with many quizzes and practical exercises to reinforce the content covered in the lectures. The expected prerequisites are shown here.

The course is split into three parts with links to further details:

1. Introduction to CPU and CPU verification (details)
2. RISC-V CPU verification (details) , which focuses on how to verify a RISC-V CPU. It uses an open-source UVM testbench, and students are expected to use it for the practical exercises.
   • There is one full course on RiscV CPU verification, but partial attendance is also possible for those already familiar with CPU verification (but not familiar with RISC-V (see column 2 “Shortened version of the course“)
3. RISC-V SoC verification (details), which focuses on the verification of an SoC which incorporates a RISC-V CPU. The primary strategy deployed here is to use the RISC-V to run programs (written in C or assembler) to verify SoC integration and functionality. It uses an open-source test bench, and students are expected to use it for the practical exercises.