Bounded Load/Store Operations

Concept

In the RISC-V Vector (RVV) extension, a bounded load/store operation is a Code Fragment composed of multiple assembler instructions that together realize a vector load/store with bounded addresses/parameters. Within the RVVTS framework, such bounded load/stores are generated via a grammar-based Instruction Sequence Generator (ISG) that extends a context-free grammar with Python-backed function symbols to obtain context-sensitive expressiveness.

First seen 7/19/2026

Last seen 7/19/2026

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Bounded Load/Store Operations

Definition

In the RISC-V Vector (RVV) extension, a bounded load/store operation is a Code Fragment consisting of multiple assembler instructions that work together to implement a single bounded vector load or store. Unlike an ordinary RVV instruction, which is encoded as one assembler line, a bounded load/store Code Fragment bundles the bounding logic together with the vector load/store instruction itself.

For example, while a Code Fragment for an RVV add operation contains a single vector add instruction, a Code Fragment for an RVV bounded load/store operation contains multiple assembler instructions to realize the bounding together with a vector load/store instruction.

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NEIGHBORHOOD

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graph · bounded load/store operations · depth=1

RELATIONSHIPS

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grammar-based ISG ← uses 90% 2e

The grammar-based ISG supports generation of bounded load/store operations.

LINKED ENTITIES

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grammar-based ISG USES Extracted graph relationship

CITATIONS

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[1] A Code Fragment for an RVV bounded load/store operation contains multiple assembler instructions to realize the bounding and a vector load/store instruction. Single Instruction Isolation for RISC-V Vector Test Failures

[2] Bounded load/store operations consist of multiple instructions dependent on each other and are an example of complex sequences that exceed the expressiveness of a pure context-free grammar. Single Instruction Isolation for RISC-V Vector Test Failures

[3] The ISG extends the context-free grammar with special function symbols associated with Python functions; calling these functions provides context-sensitive expressiveness, and the result is integrated into the generated Code Fragment. Single Instruction Isolation for RISC-V Vector Test Failures

[4] Functions in the ISG are used, for example, to generate immediate values, register allocations, valid values for CSRs, and bounded load/stores. Single Instruction Isolation for RISC-V Vector Test Failures