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Bounded Load/Store Operations

Concept WIKI v1 · 7/19/2026

In the RISC-V Vector (RVV) extension, a bounded load/store operation is a Code Fragment composed of multiple assembler instructions that together realize a vector load/store with bounded addresses/parameters. Within the RVVTS framework, such bounded load/stores are generated via a grammar-based Instruction Sequence Generator (ISG) that extends a context-free grammar with Python-backed function symbols to obtain context-sensitive expressiveness.

Bounded Load/Store Operations

Definition

In the RISC-V Vector (RVV) extension, a bounded load/store operation is a Code Fragment consisting of multiple assembler instructions that work together to implement a single bounded vector load or store. Unlike an ordinary RVV instruction, which is encoded as one assembler line, a bounded load/store Code Fragment bundles the bounding logic together with the vector load/store instruction itself.

For example, while a Code Fragment for an RVV add operation contains a single vector add instruction, a Code Fragment for an RVV bounded load/store operation contains multiple assembler instructions to realize the bounding together with a vector load/store instruction.

Why bounded load/stores are a generation challenge

Context-free grammars are highly efficient at generating syntactically valid, simple instruction sequences. However, their expressiveness is too limited for more complex, multi-instruction sequences whose values depend on each other. Generating bounded values — possibly dynamically parameterized, such as an address restricted to a specific range — is one such case. Bounded load/store operations are a more complex instance of this problem, since they consist of multiple instructions that are mutually dependent.

Generation in the grammar-based ISG

To handle bounded load/store operations (and similar cases) efficiently, the RVVTS grammar-based Instruction Sequence Generator (ISG) extends the context-free grammar with special function symbols associated with Python functions. The ISG expands such function symbols by calling the associated function, which can provide context-sensitive expressiveness. The result returned by the function is then integrated into the generated Code Fragment.

In the ISG, Python-backed functions are used for, among other things:

  • generating immediate values,
  • register allocations,
  • valid values for CSRs,
  • bounded load/stores.

Related concept

  • grammar-based ISG — the generator that uses context-free grammars extended with Python function symbols to produce bounded load/stores and other context-sensitive constructs.

References

  • Schlägl and Große, Single Instruction Isolation for RISC-V Vector Test Failures, ICCAD '24, New York, NY, USA — Sections discussing Code Fragments, the grammar-based ISG, and bounded load/store generation.

LINKED ENTITIES

1 links
grammar-based ISG USES

CITATIONS

4 sources
4 citations
[1] A Code Fragment for an RVV bounded load/store operation contains multiple assembler instructions to realize the bounding and a vector load/store instruction. Single Instruction Isolation for RISC-V Vector Test Failures
[2] Bounded load/store operations consist of multiple instructions dependent on each other and are an example of complex sequences that exceed the expressiveness of a pure context-free grammar. Single Instruction Isolation for RISC-V Vector Test Failures
[3] The ISG extends the context-free grammar with special function symbols associated with Python functions; calling these functions provides context-sensitive expressiveness, and the result is integrated into the generated Code Fragment. Single Instruction Isolation for RISC-V Vector Test Failures
[4] Functions in the ISG are used, for example, to generate immediate values, register allocations, valid values for CSRs, and bounded load/stores. Single Instruction Isolation for RISC-V Vector Test Failures