Interrupt
ConceptIn the Ibex verification flow, an interrupt is an external stimulus that causes a trap handled by dedicated interrupt handler code. ISS golden models cannot natively model interrupts, so a RISCV-DV handshaking mechanism is used together with a modified trace-log comparison to verify correct interrupt handling.
First seen 6/6/2026
Last seen 6/6/2026
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Definition
In the Ibex core verification context, an interrupt is a form of external stimulus that triggers a trap in the core. Together with debug requests and memory faults, interrupts are the principal class of asynchronous, externally-driven events that the RTL/ISS co-simulation flow must cover [chunk:9a950617-e250-431d-8371-91884e237d19].
Why ISS Models Cannot Model Interrupts
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2 connectionsInterrupts are a form of external stimulus in the co-simulation flow.
core_ibex_test_lib.sv handles interrupt assertion verification.
CITATIONS
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[1] Interrupts are a form of external stimulus in the Ibex verification flow, alongside debug requests and memory faults. Verification — Ibex Documentation 0.1.dev50+g9742d89f5
[2] ISS models can simulate traps due to exceptions but cannot model traps due to external stimulus such as interrupts, which breaks standard RTL/ISS trace log comparison. Verification — Ibex Documentation 0.1.dev50+g9742d89f5
[3] The Ibex testbench uses the RISCV-DV handshaking mechanism to verify that the core has entered the proper interrupt handler, entered Debug Mode properly, and updated any CSRs correctly. Verification — Ibex Documentation 0.1.dev50+g9742d89f5
[4] The testbench uses handshake signature address 0x8ffffffc, with API tasks provided in dv/uvm/core_ibex/tests/core_ibex_base_test.sv. Verification — Ibex Documentation 0.1.dev50+g9742d89f5
[5] The handshaking mechanism is extensively used in dv/uvm/core_ibex/tests/core_ibex_test_lib.sv to provide runtime verification for interrupt assertions, external debug requests, and memory faults. Verification — Ibex Documentation 0.1.dev50+g9742d89f5
[6] Trace log comparison is modified to compare only the final values in every register at the end of the test, because the ISS trace log does not contain execution information for interrupt handler or debug ROM code. Verification — Ibex Documentation 0.1.dev50+g9742d89f5