2026-07-17
4 items 110 entities 163 connections
Processed 30 entities and 55 relations.
Constrained-Random Verification Uniform Generation of SAT Witnesses UniGen UniWit XORSample' PAWS ApproxMC CryptoMiniSAT Hashing-Based Sampling XOR-based Hash Partitioning Independent Support Almost-Uniform Generator Approximate Model Counting Boolean CNF Formula Markov Chain Monte Carlo Sampling BDD-Based Sampling Simulation-Based Functional Verification RTL Model Test Vector Generation Tseitin Encoding Leapfrogging Heuristic Supratik Chakraborty Kuldeep S. Meel Moshe Y. Vardi Stefano Ermon Carla P. Gomes UniGen Paper (DAC 2014) r-wise Independent Hash Functions SAT Witness sharpSAT
Processed 35 entities and 42 relations.
Constrained Random Verification SystemC SCV Electronic System Level Design Testbench Automation Random Variable Random Object Constraint Inheritance Dynamic Constraints Constraint Management Inline Generators Parallel Constraint Solving BDD-based Constraint Solving SAT/SMT Solving Portfolio Approach Uniform Distribution ALU Stimulus Generation randv rand_obj rand_vec Generator metaSMT Daniel Große Finn Haedicke Hoang M. Le Rolf Drechsler University of Bremen An Advanced Constrained Random Verification Environment for SystemC Quality-Driven SystemC Design SMT-based stimuli generation in the SystemC verification library Improvements for constraint solving in the SystemC verification library Soft Constraint Hard Constraint References in Constraints Vector Constraints
Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.
source →Processed 34 entities and 57 relations.
Constrained Random Test (CRT) Directed Test Bench Test Vector Design Under Test (DUT) CRT Test Bench SystemVerilog Register Transfer Level (RTL) Instruction Abstraction Layer (IAL) Control Command Bus Macro Instruction (MI) Atomic Instruction (AI) Program Instruction Sequence Interrupt Service Routine (ISR) Instruction Sequence Noise Instruction Constrained Random Verification Order Dependent Instructions Polling Instruction Functional Coverage Program Instruction Streamer Noise Instruction Streamer Interrupt Service Instruction Streamer Custom Instruction Streamer Priority Scheduler Instruction Translator Control Bus Master BFM Module Control Bus Slave BFM Module Test Case Generator Test Manager Register Abstraction Layer (RAL) Verification Methodology Manager (VMM) Integrated Circuit (ASIC) Design Randomized Instruction Sequence Instruction Queue Control Path Verification