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Universität Bremen - Computer Architecture

An Advanced

Constrained Random Verification Environment for SystemC

Daniel Große, Finn Haedicke,

Hoang M. Le, Rolf Drechsler

Group of Computer Architecture, University of Bremen, Germany

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Universität Bremen - Computer Architecture

Outline

  1. Motivation
  2. Constraint Specification Random Variable Random Object Constraint Inheritance
  3. Dynamic Constraints Dynamic Data Structures Constraint Management References in Constraints
  4. Inline Generators usage
  5. Parallel Constraint Solving
  6. Summary

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Universität Bremen - Computer Architecture

Motivation

  • ESL design to handle complexity (abstraction!)

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Universität Bremen - Computer Architecture

Motivation

  • ESL design to handle complexity (abstraction!)
  • Widely accepted ESL language: SystemC

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Universität Bremen - Computer Architecture

Motivation

  • ESL design to handle complexity (abstraction!)
  • Widely accepted ESL language: SystemC
  • Verification dictates design costs

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Universität Bremen - Computer Architecture

Motivation

  • ESL design to handle complexity (abstraction!)
  • Widely accepted ESL language: SystemC
  • Verification dictates design costs
  • Manage verification effort by testbench automation ⇒ Constrained Random Verification (CRV)

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Universität Bremen - Computer Architecture

Motivation

  • ESL design to handle complexity (abstraction!)
  • Widely accepted ESL language: SystemC
  • Verification dictates design costs
  • Manage verification effort by testbench automation ⇒ Constrained Random Verification (CRV)
    • CRV for SystemC through SCV library

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Universität Bremen - Computer Architecture

Motivation

  • ESL design to handle complexity (abstraction!)
  • Widely accepted ESL language: SystemC
  • Verification dictates design costs
  • Manage verification effort by testbench automation ⇒ Constrained Random Verification (CRV)
    • CRV for SystemC through SCV library
    • SCV has several weaknesses

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Universität Bremen - Computer Architecture

Motivation

  • ESL design to handle complexity (abstraction!)
  • Widely accepted ESL language: SystemC
  • Verification dictates design costs
  • Manage verification effort by testbench automation ⇒ Constrained Random Verification (CRV)
    • CRV for SystemC through SCV library
    • SCV has several weaknesses
    • Development of Advanced CRV Environment

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Universität Bremen - Computer Architecture

Random Variable

randv x;

  • x: variable of built-in or SystemC type T

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Universität Bremen - Computer Architecture

Random Variable

randv x;

  • x: variable of built-in or SystemC type T
  • Simple constraints: addRange(1, r) addWeightedRange(1,r,w)

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Universität Bremen - Computer Architecture

Random Variable

randv x;

  • x: variable of built-in or SystemC type T
  • Simple constraints: addRange(1, r) addWeightedRange(1,r,w)
  • x(): symbolic variable used in complex constraints

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Universität Bremen - Computer Architecture

Random Variable

randv x;

  • x: variable of built-in or SystemC type T
  • Simple constraints: addRange(1, r) addWeightedRange(1,r,w)
  • x(): symbolic variable used in complex constraints
  • C++ operators available for x and x() (+,-,*,/%, ==, !=, <,>, >=, <=, <<, >>, &&, ||, !, ~, &, |, ^)

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Universität Bremen - Computer Architecture

Random Variable

randv x;

  • x: variable of built-in or SystemC type T
  • Simple constraints: addRange(1, r) addWeightedRange(1, r, w)
  • x(): symbolic variable used in complex constraints
  • C++ operators available for x and x() (+, -, *, /, %, ==, !=, <, >, >=, <=, <<, >>, &&, ||, !, ~, &, |, ^)

randv x;

// 30% in [0, 9] x.addWeightedRange(0, 9, 30);

// 70% in [90, 99] x.addWeightedRange(90, 99, 70);

// get value x.next();

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Universität Bremen - Computer Architecture

Random Object

rand_obj

  • a random object extends rand_obj, contains randvs and other rand_objs.

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Universität Bremen - Computer Architecture

Random Object

rand_obj

  • a random object extends rand_obj, contains randvs and other rand_objs.
  • constraint specification in constructor/later via API call

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Universität Bremen - Computer Architecture

Random Object

rand_obj

  • a random object extends rand_obj, contains randvs and other rand_objs.
  • constraint specification in constructor/later via API call
  • constraint([name,] expr): [named] hard constraint

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Universität Bremen - Computer Architecture

Random Object

rand_obj

  • a random object extends rand_obj, contains randvs and other rand_objs.
  • constraint specification in constructor/later via API call
  • constraint([name,] expr): [named] hard constraint
  • soft_constraint(expr): ignorable constraint

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Universität Bremen - Computer Architecture

Random Object

rand_obj

  • a random object extends rand_obj, contains randvs and other rand_objs.
  • constraint specification in constructor/later via API call
  • constraint([name,] expr): [named] hard constraint
  • soft_constraint(expr): ignorable constraint
  • next() invokes constraint solver, returns true on success

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Universität Bremen - Computer Architecture

Random Object

rand_obj

  • a random object extends rand_obj, contains randvs and other rand_objs.
  • constraint specification in constructor/later via API call
  • constraint([name,] expr): [named] hard constraint
  • soft_constraint(expr): ignorable constraint
  • next() invokes constraint solver, returns true on success

struct packet : public rand_obj {

randv<unsigned> src;
randv< sc_uint<16> > dest;

packet() : ... {
    constraint(src() <= 0xFFFF);

    constraint("diff",
            src() != dest());

    soft_constraint(
            dest() % 4 == 0);
}

}

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Constraint Inheritance

  • realized by C++ inheritance

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Universität Bremen - Computer Architecture

Constraint Inheritance

  • realized by C++ inheritance
  • inherit everything of the base class

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Universität Bremen - Computer Architecture

Constraint Inheritance

  • realized by C++ inheritance
  • inherit everything of the base class
  • allows to add more random variables/objects and constraints to the base class

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Universität Bremen - Computer Architecture

Constraint Inheritance

  • realized by C++ inheritance
  • inherit everything of the base class
  • allows to add more random variables/objects and constraints to the base class

struct packet1 : public packet { randv data;

packet1() : ... {
    constraint('a' &lt;= data() &amp;&amp; data()
        &lt;= 'z');
    constraint(dest_addr() % 2 == 1);
}

}

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Vector Constraints

rand_vec v;

  • no support in SCV, mimic via fixed-size arrays (inconvenient and not always possible)

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Vector Constraints

rand_vec v;

  • no support in SCV, mimic via fixed-size arrays (inconvenient and not always possible)
  • v mimics a STL vector std::vector (T built-in type)

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Universität Bremen - Computer Architecture

Vector Constraints

rand_vec v;

  • no support in SCV, mimic via fixed-size arrays (inconvenient and not always possible)
  • v mimics a STL vector std::vector (T built-in type)
  • v(): symbolic vector used in constraints

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Vector Constraints

rand_vec v;

  • no support in SCV, mimic via fixed-size arrays (inconvenient and not always possible)
  • v mimics a STL vector std::vector (T built-in type)
  • v(): symbolic vector used in constraints
  • v().size(): size of symbolic vector

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Universität Bremen - Computer Architecture

Vector Constraints

rand_vec v;

  • no support in SCV, mimic via fixed-size arrays (inconvenient and not always possible)
  • v mimics a STL vector std::vector (T built-in type)
  • v(): symbolic vector used in constraints
  • v().size(): size of symbolic vector
  • v()[_i]: symbolic element (_i predefined constant)

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Universität Bremen - Computer Architecture

Vector Constraints

rand_vec v;

  • no support in SCV, mimic via fixed-size arrays (inconvenient and not always possible)
  • v mimics a STL vector std::vector (T built-in type)
  • v(): symbolic vector used in constraints
  • v().size(): size of symbolic vector
  • v()[_i]: symbolic element (_i predefined constant)
  • v()[_i-c]: previous element relative to v()[_i] (c > 0)

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Universität Bremen - Computer Architecture

Vector Constraints

rand_vec v;

  • no support in SCV, mimic via fixed-size arrays (inconvenient and not always possible)
  • v mimics a STL vector std::vector (T built-in type)
  • v(): symbolic vector used in constraints
  • v().size(): size of symbolic vector
  • v()[_i]: symbolic element (_i predefined constant)
  • v()[_i-c]: previous element relative to v()[_i] (c > 0)
  • constraint.foreach and constraint.soft_foreach to build constraints over the elements

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Vector Constraints - Example

struct packet2 : public packet { rand_vec data;

packet2() : ... {
    constraint(data().size() % 4 == 0);
    constraint(data().size() &lt; 100);

    // data[0] upper case
    constraint.foreach(data, _i,
        IF_THEN(_i == 0, 'A' &lt;= data()[_i] &amp;&amp; data()[_i] &lt;= 'Z'));
    // the rest lower case
    constraint.foreach(data, _i,
        IF_THEN(_i != 0, 'a' &lt;= data()[_i] &amp;&amp; data()[_i] &lt;= 'z'));
    // forbid aa, ab and ba
    constraint.soft_foreach(data, _i,
        data()[_i] + data()[_i-1] &gt; 'a' + 'b');
}

};

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Constraint Management

  • Enable/disable specific constraints during verification process

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Constraint Management

  • Enable/disable specific constraints during verification process
  • Not available in SCV, mimic via auxiliary variables and implication constraints (inconvenient and inefficient)

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Universität Bremen - Computer Architecture

Constraint Management

  • Enable/disable specific constraints during verification process
  • Not available in SCV, mimic via auxiliary variables and implication constraints (inconvenient and inefficient)
  • Supported via named constraints constraint(name, expr).

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Universität Bremen - Computer Architecture

Constraint Management

  • Enable/disable specific constraints during verification process
  • Not available in SCV, mimic via auxiliary variables and implication constraints (inconvenient and inefficient)
  • Supported via named constraints constraint(name, expr).
  • API: enable_constraint(name) and disable_constraint(name) of rand_obj

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Universität Bremen - Computer Architecture

Constraint Management

  • Enable/disable specific constraints during verification process
  • Not available in SCV, mimic via auxiliary variables and implication constraints (inconvenient and inefficient)
  • Supported via named constraints constraint(name, expr).
  • API: enable_constraint(name) and disable_constraint(name) of rand_obj
  • Disabled constraints have no effect in the randomization via next() until enabled again

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References

  • Randomization depends on dynamically changing environment state

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Universität Bremen - Computer Architecture

References

  • Randomization depends on dynamically changing environment state
  • In SCV inefficient and tedious (additional variables, manual update)

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Universität Bremen - Computer Architecture

References

  • Randomization depends on dynamically changing environment state
  • In SCV inefficient and tedious (additional variables, manual update)
  • Here via reference(x): link a C++ variable x to a symbolic variable used in constraints

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References

  • Randomization depends on dynamically changing environment state
  • In SCV inefficient and tedious (additional variables, manual update)
  • Here via reference(x): link a C++ variable x to a symbolic variable used in constraints
  • Each call to next() uses actual value of x

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Universität Bremen - Computer Architecture

References

  • Randomization depends on dynamically changing environment state
  • In SCV inefficient and tedious (additional variables, manual update)
  • Here via reference(x): link a C++ variable x to a symbolic variable used in constraints
  • Each call to next() uses actual value of x

struct packet3 : public packet { rand_vec data;

packet3(int &expected_max_size) : ... {
    constraint(data().size() % 4 == 0);

    constraint(data().size() &lt;=
        reference(expected_max_size));
    // data[0] upper case
    ...
}

};

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Inline Generators

  • Constraint specification without random_obj

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Universität Bremen - Computer Architecture

Inline Generators

  • Constraint specification without random_obj
  • Based on Generator object

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Universität Bremen - Computer Architecture

Inline Generators

  • Constraint specification without random_obj
  • Based on Generator object
  • Usable anywhere independent of other constraints

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Universität Bremen - Computer Architecture

Inline Generators

  • Constraint specification without random_obj
  • Based on Generator object
  • Usable anywhere independent of other constraints
  • All features except for inheritance

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Universität Bremen - Computer Architecture

Inline Generators

  • Constraint specification without random_obj
  • Based on Generator object
  • Usable anywhere independent of other constraints
  • All features except for inheritance

randv x,y; Generator gen;

gen( x() < y() ); gen( x() > 100 || y() < 50);

if (gen.next()) run_test(x,y);

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Incremental Generator usage

  • Incrementally add new constraints

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Universität Bremen - Computer Architecture

Incremental Generator usage

  • Incrementally add new constraints
  • Previous constraints stay valid

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Universität Bremen - Computer Architecture

Incremental Generator usage

  • Incrementally add new constraints
  • Previous constraints stay valid
  • Trigger specific behavior after generic behavior executed

randv x,y; Generator gen; gen(x != y) for (int i =0 ; i < n; ++i) { gen.next(); run_test(x,y); }

gen( x*x == y ); for (...) { gen.next(); run_test(x,y) ; }

gen( y%2 == 0 ); for (...) { gen.next(); run_test(x,y) ; }

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Parallel Constraint Solving

  • SCV: Limits in constraint complexity due to BDD-based constraint-solving

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Parallel Constraint Solving

  • SCV: Limits in constraint complexity due to BDD-based constraint-solving
  • Alternatives: SAT/SMT

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Universität Bremen - Computer Architecture

Parallel Constraint Solving

  • SCV: Limits in constraint complexity due to BDD-based constraint-solving
  • Alternatives: SAT/SMT
  • But: BDD guarantees uniform distribution, hard for SAT/SMT

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Universität Bremen - Computer Architecture

Parallel Constraint Solving

  • SCV: Limits in constraint complexity due to BDD-based constraint-solving
  • Alternatives: SAT/SMT
  • But: BDD guarantees uniform distribution, hard for SAT/SMT
  • Here: Portfolio approach

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Universität Bremen - Computer Architecture

Parallel Constraint Solving

  • SCV: Limits in constraint complexity due to BDD-based constraint-solving

  • Alternatives: SAT/SMT

  • But: BDD guarantees uniform distribution, hard for SAT/SMT

  • Here: Portfolio approach

  • Multi-threaded

  • SMT provides fast solutions

  • BDD provides uniform distribution

  • use BDD once created

img-0.jpeg

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Parallel Constraint Solving (2)

  • Comparison to SCV
  • Focus: How fast can the solutions be generated?
  • Example: Constraint inputs of ALU such that output is computed w/o overflow or divide-by-zero exceptions

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Parallel Constraint Solving (2)

  • Comparison to SCV
  • Focus: How fast can the solutions be generated?
  • Example: Constraint inputs of ALU such that output is computed w/o overflow or divide-by-zero exceptions

randv< sc_bv<2> > op; randv< sc_uint<16> > a; randv< sc_uint<16> > b;

constraint( op() != 0 || 65535 >= a() + b() );

constraint( op() != 1 || (65535 >= a() - b() && b() <= a() ) );

constraint( op() != 2 || 65535 >= a() * b() );

constraint( op() != 3 || b() != 0 );

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Universität Bremen - Computer Architecture

Parallel Constraint Solving (2)

  • Comparison to SCV

  • Focus: How fast can the solutions be generated?

  • Example: Constraint inputs of ALU such that output is computed w/o overflow or divide-by-zero exceptions

  • run-time in sections for first/all stimuli

  • SCV 1.0e 32 bit vs. new approach

tbl-0.md

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Summary and Future Work

  • Advanced Constraint Random Verification Environment
  • Natural C++ Syntax, easy to use API
  • Dynamic constraints/constraint management
  • Parallel constraint solving with advanced decision engines

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Summary and Future Work

  • Advanced Constraint Random Verification Environment
  • Natural C++ Syntax, easy to use API
  • Dynamic constraints/constraint management
  • Parallel constraint solving with advanced decision engines
  • Extended support for dynamic data structures
  • SMT distribution quality
  • Automated constraint debugging

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Universität Bremen - Computer Architecture

Summary and Future Work

  • Advanced Constraint Random Verification Environment

  • Natural C++ Syntax, easy to use API

  • Dynamic constraints/constraint management

  • Parallel constraint solving with advanced decision engines

  • Extended support for dynamic data structures

  • SMT distribution quality

  • Automated constraint debugging

Thank you for your attention.

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References I

[1] OSCI, “SystemC,” 2011, available at http://www.systemc.org.

[2] IEEE Standard SystemC Language Reference Manual, IEEE Std. 1666, 2005.

[3] J. Yuan, C. Pixley, and A. Aziz, Constraint-based Verification. Springer, 2006.

[4] SystemC Verification Standard Specification Version 1.0e, SystemC Verification Working Group, http://www.systemc.org, 2003.

[5] J. Rose and S. Swan, SCV Randomization Version 1.0, 2003.

[6] C. N. Ip and S. Swan, “A tutorial introduction on the new SystemC verification standard,” www.systemc.org, White Paper, 2003.

[7] F. Haedicke, S. Frehse, G. Fey, D. Große, and R. Drechsler, “metaSMT: Focus on your application not on solver integration,” in DIFTS’11: 1st International workshop on design and implementation of formal tools and systems, 2011.

[8] D. Große and R. Drechsler, Quality-Driven SystemC Design. Springer, 2010.

[9] D. Große, R. Ebendt, and R. Drechsler, “Improvements for constraint solving in the SystemC verification library,” in ACM Great Lakes Symposium on VLSI, 2007, pp. 493–496.

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References II

[10] D. Große, R. Wille, R. Siegmund, and R. Drechsler, “Debugging contradictory constraints in constraint-based random simulation,” in Languages for Embedded Systems and their Applications: Selected Contributions on Specification, Design, and Verification from FDL’08, M. Radetzki, Ed. Springer, 2009, pp. 273–290.

[11] R. Wille, D. Große, F. Haedicke, and R. Drechsler, “SMT-based stimuli generation in the SystemC verification library,” in Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s: Selected Contributions on Specification, Design, and Verification from FDL 2009, D. Borrione, Ed. Springer, 2010, pp. 227–244.

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