2026-07-28
6 items 188 entities 216 connections
Processed 4 entities and 4 relations.
Processed 29 entities and 36 relations.
BOOM Spike riscv-dv RISC-V ISA extension directed tests random stress test differential verification lockstep cosimulation base-ISA regression suite LLM-in-the-loop RTL generation CosimNode isa_tests riscv_dv_target_crypto riscv_dv_target_zicond instructions.json RISC-V custom instruction (RV64X) Bit-Manipulation extension (Zba/Zbb/Zbc/Zbs) scalar Cryptography extension (Zbk*/Zkn*) Zicond extension riscv-opcodes Xcelium prebuilt stress binaries run_vext_loop CHIA PPA analysis Chipyard RTL CHIA arXiv paper (arXiv:2606.27350) cospike
Processed 39 entities and 53 relations.
A Unified Methodology for Pre-Silicon Verification and Post-Silicon Validation Allon Adir Shady Copty Shimon Landa Charles Meissner John Schumann Amir Nahir Gil Shurek Avi Ziv IBM Server and Technology Group IBM Research - Haifa pre-silicon verification post-silicon validation coverage-driven verification verification plan test-template random stimuli generation functional coverage Threadmill IBM POWER7 GenesysPro constraint satisfaction problem reference model bare-metal exerciser hardware acceleration platform software simulation platform directed random test generation Design Under Verification multi-pass comparison checking architectural model Exercisers on Accelerators IBM POWER5 Y. Naveh M. Rimon test-template language observability testing knowledge static test generation register dependency
Processed 70 entities and 70 relations.
UVM environment for RISC-V processors Leonardo Barraco Edgar Ernesto Sanchez Sanchez Annachiara Ruospo Politecnico di Torino ETH Zürich Integrated Systems Laboratory University of Bologna Energy-efficient Embedded Systems Group Functional Verification Coverage Driven Verification Stimulus Generation Random Constrained Stimulus Generation Fault Injection Illegal Instruction Injection Interrupt Request Injection Asynchronous Reset Injection Code Coverage Statement Coverage Expression Coverage FSM Coverage Instruction Set Coverage Transaction Level Modeling Reference Model Check Corner Case Verification Universal Verification Methodology Simulation-Based Verification UVM Testbench RVGEN2.py RV Generator ISA Database UVM Env Configurator riscv-dv Processor-UVM-Verification SPIKE ISS Imperas OVPsim Western Digital Whisper ISS SAIL_RISCV ISS Instruction Set Architecture RISC-V ISA RV32I Base Integer Instruction Set M Extension Integer Multiplication and Division F Extension Single-Precision Floating-Point C Extension Compressed Instructions Xpulp Proprietary Extension Post-Incrementing Load and Store Instructions Hardware Loops ALU Extension Vectorial Instructions CSR Instructions Test Vector Generation VLSI Design Flow Verification Plan RTL Implementation Instruction Stream Generation Instruction Set Simulator processor_interface.sv processor_interface_out.sv riscv_core.sv data_ram.sv ISS.yaml UVM Sequence UVM Agent UVM Scoreboard UVM Driver UVM Monitor SystemVerilog Constraints Python Script RV32IMFCXpulp RI5CY Processor Anish Gupta Universal Verification Methodology
Processed 32 entities and 38 relations.
Input and Output Generation for the Verification of ALU: a Use Case Ondrej Cekan Richard Panek Zdenek Kotasek Brno University of Technology random stimuli generation functional verification probabilistic constrained grammar probabilistic context-free grammar arithmetic-logic unit stimulus generation framework expected output generation constrained random simulation code coverage production rules grammar constraints addition with carry operation bitwise operations carry bit propagation reference model USG (Universal Stimuli Generator) ModelSim MicroGP RISC processor FPGA test vectors application-specific integrated circuit digital signal processor Mentor Graphics J. Podivinsky G. Squillero fault tolerance