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2026-07-29

3 items 68 entities 82 connections

[PATCH 1/3] trans_rvv.c.inc: write CSRs must call mark_vs_dirty() too

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Processed 16 entities and 21 relations.

QEMU RISC-V Vector Extension mstatus.VS vector CSR state vstart CSR mark_vs_dirty trans_rvv.c.inc vector_helper.c ldst_us_trans ldst_stride_trans ldst_index_trans ldst_whole_trans translation-time vector context status Daniel Henrique Barboza Ventana Micro Systems RISC-V

[06/11] target/riscv: Update CSR xtvec in CLIC mode - Patchwork

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Processed 24 entities and 35 relations.

RISC-V CLIC CSR MTVT STVT MTVEC STVEC Trap Vector Table Interrupt Handling Mode WARL QEMU CPUArchState CPURISCVState read_mtvt write_mtvt read_stvt write_stvt write_mtvec write_stvec csr_ops XTVEC_MODE XTVEC_NBASE Machine-mode Interrupts Supervisor-mode Interrupts

[PATCH RFC 2/6] riscv: perf: Add Control transfer records CSR definations. — Linux Perf Users

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Processed 28 entities and 26 relations.

RISC-V Control Transfer Records Control and Status Register M-mode S-mode VS-mode Control Transfer Record Depth Control Transfer Record Status Branch Prediction Return Address Stack Emulation Indirect Call Direct Call Indirect Jump Direct Jump Co-routine Swap Exception Handling Interrupt Handling Trap Return Taken Branch Nontaken Branch arch/riscv/include/asm/csr.h CSR_MCTRCTL CSR_SCTRCTL CSR_SCTRSTATUS CSR_SCTRDEPTH CSR_VSCTRCTL RISC-V International Rajnesh Kanwal RISC-V