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STIMSMITH

NISA-DV

Tool
First seen 7/28/2026
Last seen 7/28/2026
Evidence 1 chunks

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RELATIONSHIPS

10 connections
chip design verification implements → 97% 1e
NISA-DV is a verification framework that implements chip design verification for neuromorphic ISA extensions.
random test uses → 97% 1e
NISA-DV includes random test as one of its verification methods.
Directed Test uses → 97% 1e
NISA-DV includes directed test as one of its verification methods.
boundary condition test uses → 97% 1e
NISA-DV includes boundary condition test as one of its verification methods.
random constrained test uses → 95% 1e
NISA-DV uses a combination of random constrained tests with directed feedback.
NeuroRVCore evaluates → 96% 1e
NISA-DV is used to evaluate and verify the NeuroRVCore neuromorphic processor.
riscv-dv compares with → 96% 1e
NISA-DV is compared against RISCV-DV as a baseline random verification method.
neuromorphic ISA implements → 97% 1e
NISA-DV is specifically designed to verify neuromorphic ISA extensions.
block coverage evaluates → 95% 1e
NISA-DV measures block coverage as a verification metric, achieving 8.34% improvement.
toggle coverage evaluates → 95% 1e
NISA-DV measures toggle coverage as a verification metric, achieving 29.63% improvement.