An effective and efficient verification is a fundamental part of the chip design process, and it becomes more important and critical as the latter gets more complex. The efficacy of classical verification methods such as random test is significantly diminished when applied to emerging architectures such as neuromorphic processors due to the lack of corresponding decoding for instruction encoding and computational characteristics. Therefore, this paper proposes NISA-DV (Design verification for neuromorphic ISA), a verification framework to verify RISC-V-based neuromorphic ISA extensions, including random test, directed test, and boundary condition test methods. Using a combination of random constrained tests with directed feedback and manually designed directed tests, we obtain 8.34% block coverage and 29.63% toggle coverage improvement on the NeuroRVCore sample neuromorphic processor, compared to the random method using only RISCV-DV.