ALU Extension

Concept

The ALU Extension is a PULP-proprietary RISC-V instruction set extension, part of the Xpulp proprietary extension, that augments the RI5CY core's ALU with Bit-Manipulation, General ALU, and Immediate Branching instructions. Its detailed instruction encodings are documented in Appendix A of the source reference.

First seen 7/28/2026

Last seen 7/28/2026

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Overview

The ALU Extension is one of the instruction-set extensions grouped under the Xpulp Proprietary Extension of the RISC-V based RI5CY processor core. RI5CY is an open-source 32-bit, 4-stage pipelined processor (IF, ID, EX, WB) developed through a collaboration between ETH University and the University of Bologna and released under the SolderPad open-source license as part of the PULP project, which targets energy efficiency by minimizing power consumption during idle states. The full RI5CY ISA is identified as RV32IMFCXpulp, comprising:

I — Base Integer Instruction Set
M — Integer Multiplication and Division Instruction Set
F — Single-precision Floating-point Instruction Set
C — Compressed Instruction Set
Xpulp — PULP-specific proprietary extensions, which include:
- Post-incrementing load and stores
- Multiply and accumulate extension
- ALU Extension
- Hardware Loops

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Xpulp Proprietary Extension part of → 100% 2e

ALU extensions are part of the Xpulp proprietary extension.

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CITATIONS

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[1] ALU Extension is part of the Xpulp proprietary extension on the RI5CY core (RV32IMFCXpulp). UVM environment for RISC-V processors

[2] RI5CY is an open-source 32-bit, 4-stage pipelined processor (IF, ID, EX, WB) from a collaboration between ETH University and the University of Bologna, released under the SolderPad license, focused on energy efficiency. UVM environment for RISC-V processors

[3] The ALU Extension's instruction set is divided into Bit-Manipulation instructions, General ALU instructions, and Immediate Branching instructions. UVM environment for RISC-V processors

[4] Because the ALU Extension contains a large number of instructions, their encoding tables are reported in Appendix A. UVM environment for RISC-V processors

[5] Appendix A of the reference document is dedicated to the ALU Extension and is organized into A.1 Bit Manipulation Operations, A.2 General ALU Operations, A.3 Immediate Branching, and A.4 MAC Operations, with corresponding encoding tables A.1–A.8. UVM environment for RISC-V processors

[6] Section 2.1.6 'ALU Extension' appears in the table of contents at page 23 of the reference document. UVM environment for RISC-V processors