base-ISA regression suite

Concept

In the CHIA RISC-V extensions case study, the base-ISA regression suite is the third verification stage applied to every candidate extension: after directed per-instruction tests pass, the full base-ISA test suite is run against the modified BOOM core to ensure the proposed ISA edit does not break unrelated instructions. Only after both the directed tests and this regression suite pass does the flow advance to riscv-dv stress co-simulation against Spike, and ultimately to PPA synthesis.

First seen 7/28/2026

Last seen 7/28/2026

Evidence 1 chunks

Wiki v1

WIKI

Definition

The base-ISA regression suite is, within the CHIA riscv_extensions case study, the stage-3 verification step applied to each LLM-proposed ISA extension in a BOOM core. It runs the full riscv-test suite for the unmodified base ISA against the device under test (DUT), so a candidate extension that adds or alters Chisel cannot silently break ordinary instructions.

Role in the per-extension loop

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

1 connections

CHIA ← uses 97% 1e

CHIA checks functional correctness on the full base-ISA regression suite to prevent regressions.

LINKED ENTITIES

1 links

CHIA USES Extracted graph relationship

CITATIONS

4 sources

4 citations — click to collapse

[1] The base-ISA regression suite is stage 3 of the per-extension loop, run after the directed per-instruction tests and before riscv-dv stress co-simulation and PPA synthesis. RISC-V ISA Extension Implementation — CHIA main documentation

[2] A regression failure feeds back to the implement-LLM; only when both the directed tests and the full base-ISA regression suite pass does the stress phase begin. RISC-V ISA Extension Implementation — CHIA main documentation

[3] The base-ISA regression suite checks the full riscv-test suite against the DUT to ensure the proposed ISA edit does not break unrelated instructions. RISC-V ISA Extension Implementation — CHIA main documentation

[4] The suite is verified differentially against Spike compiled into the simulator as cospike, which checks every committed instruction and fails at the first architectural mismatch. RISC-V ISA Extension Implementation — CHIA main documentation