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base-ISA regression suite

Concept WIKI v1 · 7/28/2026

In the CHIA RISC-V extensions case study, the base-ISA regression suite is the third verification stage applied to every candidate extension: after directed per-instruction tests pass, the full base-ISA test suite is run against the modified BOOM core to ensure the proposed ISA edit does not break unrelated instructions. Only after both the directed tests and this regression suite pass does the flow advance to riscv-dv stress co-simulation against Spike, and ultimately to PPA synthesis.

Definition

The base-ISA regression suite is, within the CHIA riscv_extensions case study, the stage-3 verification step applied to each LLM-proposed ISA extension in a BOOM core. It runs the full riscv-test suite for the unmodified base ISA against the device under test (DUT), so a candidate extension that adds or alters Chisel cannot silently break ordinary instructions.

Role in the per-extension loop

The driver run_vext_loop() performs verification in a strict order:

  1. Directed tests — one program per instruction in the extension, judged differentially against Spike.
  2. Base-ISA regression — the full riscv-test suite is run on the DUT.
  3. Stress test — riscv-dv-generated programs mixing the extension and ordinary code, co-simulated against Spike in lockstep for several million instructions.
  4. PPA synthesis — BoomTile with and without the extension to measure area/timing cost.

The regression suite is the gate that protects the stress phase. If it fails, the edit feeds straight back to the implement-LLM; if it passes, the stress test (and later synthesis) is allowed to proceed. A regression failure caught here means a divergence is detected the cycle it happens, because Spike is compiled into the simulator as cospike and checks every committed instruction.

How it is checked

Like every other verification stage in the loop, the base-ISA regression suite is run with the differential, lockstep pattern: the DUT executes while the embedded Spike oracle decodes each committed instruction using the DUT's own ISA string. The first architectural mismatch fails the regression, again catching bugs the cycle they occur rather than inferring them from final results.

Artifacts produced

When the per-extension flow converges, each sweep archived in the log DB contains, alongside the BOOM diff, LLM transcripts, per-test simulation logs, and PPA deltas, the artifacts accumulated during this stage. A regression-stage failure becomes feedback for the implement-LLM and triggers a fresh clean stress run as the bar to converge.

Related concepts

  • CHIA — the case study and tooling that orchestrates the loop that contains this regression stage.
  • Spike — the golden ISA simulator compiled into cospike, used as the differential oracle for this and every other verification stage.
  • BOOM — the DUT core being modified; the regression suite guards against it regressing on instructions outside the extension under test.
  • riscv-test — the test suite used as the base-ISA regression input.
  • riscv-dv stress test — the subsequent stage that only runs once this regression suite passes.
  • PPA synthesis — the final stage that only runs once stress testing converges after the regression stage has passed.

LINKED ENTITIES

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CITATIONS

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4 citations
[1] The base-ISA regression suite is stage 3 of the per-extension loop, run after the directed per-instruction tests and before riscv-dv stress co-simulation and PPA synthesis. RISC-V ISA Extension Implementation — CHIA main documentation
[2] A regression failure feeds back to the implement-LLM; only when both the directed tests and the full base-ISA regression suite pass does the stress phase begin. RISC-V ISA Extension Implementation — CHIA main documentation
[3] The base-ISA regression suite checks the full riscv-test suite against the DUT to ensure the proposed ISA edit does not break unrelated instructions. RISC-V ISA Extension Implementation — CHIA main documentation
[4] The suite is verified differentially against Spike compiled into the simulator as cospike, which checks every committed instruction and fails at the first architectural mismatch. RISC-V ISA Extension Implementation — CHIA main documentation