Bit-Manipulation extension (Zba/Zbb/Zbc/Zbs)

Concept

The RISC-V Bit-Manipulation extension (Zba/Zbb/Zbc/Zbs) is a ratified RISC-V ISA extension implemented and verified end-to-end by CHIA on a MegaBOOM core using an LLM-in-the-loop methodology. In the CHIA `riscv_extensions` case study, it is one of three target extensions (alongside scalar cryptography and Zicond) implemented in BOOM Chisel and proven correct via differential cosimulation against Spike, with directed per-instruction tests, base-ISA regression, and riscv-dv stress testing.

First seen 7/28/2026

Last seen 7/28/2026

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Bit-Manipulation extension (Zba/Zbb/Zbc/Zbs)

The Bit-Manipulation extension (commonly grouped under the Zb* umbrella — Zba, Zbb, Zbc, Zbs) is a standard RISC-V ISA extension that adds instructions for bit-level and small-integer arithmetic operations. In the CHIA riscv_extensions case study, it is treated as a first-class target extension alongside scalar Cryptography (Zbk*/Zkn*) and Zicond.

Role in the CHIA riscv_extensions flow

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CHIA ← evaluates 98% 1e

CHIA implemented and verified the Bit-Manipulation extension on a MegaBOOM core.

CHIA arXiv paper (arXiv:2606.27350) ← mentions 95% 1e

The CHIA paper reports results for the Bit-Manipulation extension.

LINKED ENTITIES

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CHIA EVALUATES The Bit-Manipulation extension is implemented and verified end-to-end by the CHIA `riscv_extensions` case-study flow (which is part of CHIA).

CHIA arXiv paper (arXiv:2606.27350) MENTIONS Extracted graph relationship

CITATIONS

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7 citations — click to expand

[1] Bit-Manipulation (Zba/Zbb/Zbc/Zbs) is one of three extensions — alongside scalar Cryptography and Zicond — implemented and verified on a MegaBOOM core in the CHIA riscv_extensions case study. RISC-V ISA Extension Implementation — CHIA main documentation

[2] CHIA registers Bit-Manipulation as the 'bitmanip' extension with the ISA suffix '_zba_zbb_zbc_zbs'. RISC-V ISA Extension Implementation — CHIA main documentation

[3] riscv-dv can generate bitmanip natively; the crypto and Zicond extensions require custom riscv-dv targets. RISC-V ISA Extension Implementation — CHIA main documentation

[4] Verification of Bit-Manipulation uses directed per-instruction tests (built from specs/bitmanip/instructions.json), the full base-ISA riscv-test regression, and riscv-dv stress tests co-simulated against Spike. RISC-V ISA Extension Implementation — CHIA main documentation

[5] Spike is compiled into the simulator (cospike) and checks every committed instruction against the architectural specification; CosimNode runs one ELF in lockstep against the Spike oracle. RISC-V ISA Extension Implementation — CHIA main documentation

[6] The LLM-in-the-loop implements the extension by editing BOOM Chisel guided by the ratified spec; a stress divergence triggers a debug LLM that repairs the RTL, after which the verify-then-stress loop restarts. RISC-V ISA Extension Implementation — CHIA main documentation

[7] Reported results: the three implemented extensions (Bit-Manipulation, scalar Cryptography, Zicond) deliver ~5.6% and ~3.5% speedups (up to 10× on OpenSSL crypto), no timing regressions, and modest area overhead in SkyWater 130nm. RISC-V ISA Extension Implementation — CHIA main documentation