2026-06-06
5 items 225 entities 296 connections
Processed 54 entities and 76 relations.
MorFuzz Instruction Morphing Stimulus Template Synchronizable Co-simulation State Synchronization Field Level Mutation Semantic Level Mutation Instruction Shuffle Coverage-Guided Fuzzing Runtime Instruction Morphing Magic Instruction Generation Constrained Random Instruction Generation Static Formal Verification Simulation-Based Verification RTL Simulation Processor Fuzzing RISC-V ISA Co-simulation Control Register Coverage Fuzzing Execution Environment Fuzzing Payload Morpher Testing Block Watchpoint Instruction Golden Reference Model Implementation Differences Sequence Pattern Type Pool Morphing Map DifuzzRTL TheHuzz riscv-dv riscv-torture spike Synopsys VCS starship SoC generator FIRRTL CVA6 Rocket BOOM MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation Jinyan Xu Yiyuan Liu Sirui He Haoran Lin Yajin Zhou Cong Wang Zhejiang University City University of Hong Kong UC Berkeley Instruction Stream Generation Hardware Bug Detection Mux Coverage Hardware Behavior Coverage
DiffTest-H: Toward Semantic-Aware Communication in Hardware-Accelerated Processor Verification
source →Processed 59 entities and 68 relations.
DiffTest-H Kunlin You Yinan Xu Kehan Feng Luoshan Cai Yaoyang Zhou Yungang Bao State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences Beijing Institute of Open Source Chip co-simulation design under test (DUT) golden reference model (REF) non-deterministic events (NDEs) verification events communication overhead hardware-software communication structural semantics order semantics behavioral semantics instruction-level debuggability Batch (tight packing of verification events) Squash (order-decoupled fusion) Replay (lightweight debugging by event retransmission) event fusion hardware-software parallelism (non-blocking transmission) differencing (event field delta compression) multi-level packing strategy LogGP model DiffTest XiangShan NutShell Verilator Synopsys VCS Spike (ISS) NEMU Cadence Palladium Xilinx VU19P FPGA Fromajo RISC-V RTL simulation FPGA prototyping hardware emulation DPI-C interface instruction commit register update memory access (MMIO) cache coherence verification TLB operations ISA checker monitor unit token-based management (replay tokens) snapshot debugging compensation-based REF revert Chisel HDL XDMA protocol GFIFO (emulator non-blocking primitive) DUT trace dumping and reloading out-of-order processor vector/hypervisor extensions
Processed 25 entities and 29 relations.
RTL/ISS co-simulation register writeback comparison trace log golden model ISS external stimulus interrupt debug request Debug Mode CSR handshaking mechanism signature address debug ROM trap handler memory fault RISCV-DV Ibex RTL simulation instruction-set simulation core_ibex_base_test.sv core_ibex_test_lib.sv Makefile UVM testbench RISC-V lowRISC Google
Processed 63 entities and 90 relations.
Tandem Simulation RTL Co-simulation Instruction Set Architecture (ISA) Instruction-Level Abstraction (ILA) Instruction-Level Execution Model (ILEM) RTL-Based Execution Model (RTEM) Cross-Level Execution Model (CLEM) Architectural Variable (AV) AV-Check AV-Swap Refinement Map Conformance Testing Jump-Starting (Warm-Up Simulation) Checkpoint Map Instruction Map AV Map Cold Start Micro-Architectural Variables Simulation-Based Testing RTL (Register Transfer Level) RISC-V Memory-Mapped Input/Output (MMIO) Testbench Instruction-by-Instruction Checking System-on-Chip (SoC) High-Level Synthesis (HLS) Transaction-Level Model (TLM) Decode Function State Update Function Child-ILA (Child Instructions) ILAtor ILAng Verilator Tandem Generator AV-Comparator AV-Converter Instruction Monitor Dromajo RISC-V ISA Co-simulator Bluespec System Verilog Chisel Halide SystemC AES ILA Model AES-RTL (Block Implementation) AES-RTL (Round Implementation) GaussianBlur RTL FlexNLP RTL PicoRV32 (Pico) Piccolo RISC-V Core Rocket Core RISC-V ILA Model Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models Yue Xing Aarti Gupta Sharad Malik Princeton University DARPA Esperanto Technology Bug Detection Formal Verification Test Stimulus Generation Random Test Input Generation Program Counter (Auxiliary for Accelerator)
Processed 24 entities and 33 relations.
Nexus-AM NEMU Difftest ChiselDB TL-Test LightSSS XiangShan ISA co-simulation bare metal runtime constrained random test generation cache coherence verification trace-driven simulation waveform dump DPI-C TileLink protocol architectural state comparison RTL RISC-V coremark workload emu riscv64-nemu-interpreter Spike QEMU SQLite3