debug ROM

Concept

In the context of the Ibex core verification flow, the debug ROM refers to code that is executed by the RTL core but is not modeled by the golden-model ISS (Instruction Set Simulator). It is invoked when the core handles external stimulus such as debug requests, and its presence constrains how the end-of-test register writeback comparison is performed.

First seen 6/6/2026

Last seen 6/6/2026

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Overview

In the Ibex core's end-to-end RTL/ISS co-simulation verification flow, the debug ROM is a region of code whose execution is carried out by the RTL core but which the chosen golden-model ISS does not simulate. It is one of the classes of code — alongside interrupt handler (trap handler) code — that the ISS trace log does not contain execution information for.

Role in the verification flow

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register writeback comparison ← uses 1e

Register writeback comparison must account for code executed in the debug ROM being absent from the ISS trace log.

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CITATIONS

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4 citations — click to collapse

[1] The ISS trace log will not contain any execution information in the debug ROM or in any interrupt handler code. Verification — Ibex Documentation

[2] Comparing every register write performed during the entire simulation will lead to an incorrect result since the ISS trace log will not contain any execution information in the debug ROM or in any interrupt handler code. Verification — Ibex Documentation

[3] Any code executed in the debug ROM and trap handlers should not corrupt register state in the rest of the program, which is why only the final values contained in every register at the end of the test are compared against each other. Verification — Ibex Documentation

[4] ISS models can simulate traps due to exceptions, but cannot model traps due to external stimulus such as interrupts and debug requests, so the debug ROM is exercised by the RTL but not the ISS. Verification — Ibex Documentation