external stimulus — STIMSMITH

External Stimulus (Ibex Verification)

Concept

In the Ibex verification flow, an external stimulus is an event originating outside the core (such as interrupts, debug requests, and memory faults) that causes the core to take a trap or enter Debug Mode. ISS golden models cannot natively model traps due to external stimulus, so Ibex relies on the RISCV-DV handshaking mechanism and a modified final-state register comparison to verify these scenarios.

First seen 6/6/2026

Last seen 6/6/2026

Evidence 1 chunks

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Overview

In the Ibex end-to-end RTL/ISS co-simulation flow, an external stimulus refers to a triggering event that is not produced by the instruction stream itself but arrives from outside the core during execution. Typical examples of external stimulus in this context are:

Interrupts
Debug requests
Memory faults

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NEIGHBORHOOD

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RELATIONSHIPS

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interrupt part of → 1e

Interrupts are a form of external stimulus in the co-simulation flow.

debug request part of → 1e

Debug requests are a form of external stimulus in the co-simulation flow.

core_ibex_test_lib.sv ← uses 1e

core_ibex_test_lib.sv uses the handshaking mechanism to verify external debug requests, interrupt assertions, and memory faults.

LINKED ENTITIES

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CITATIONS

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4 citations — click to collapse

[1] External stimulus (such as interrupts and debug requests) breaks the default register-writeback trace-log comparison because ISS models can simulate exception traps but cannot model traps due to external stimulus. Verification — Ibex Documentation

[2] Ibex uses the RISCV-DV instruction generator's handshaking mechanism, with signature address 0x8ffffffc, to let the core send status information to the testbench so it can verify correct interrupt handler entry, Debug Mode entry, and CSR updates under external stimulus. Verification — Ibex Documentation

[3] Integration API tasks for the handshake are provided in core_ibex_base_test.sv, and example usage of the handshake in real simulations is in core_ibex_test_lib.sv; the mechanism is extensively used to verify external debug requests, interrupt assertions, and memory faults. Verification — Ibex Documentation

[4] When external stimulus is involved, Ibex falls back to comparing only the final register values at the end of the test, because the ISS trace log does not contain execution information from the debug ROM or interrupt handler code, and those regions should not corrupt main-program register state. Verification — Ibex Documentation