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External Stimulus (Ibex Verification)

Concept WIKI v1 · 6/6/2026

In the Ibex verification flow, an external stimulus is an event originating outside the core (such as interrupts, debug requests, and memory faults) that causes the core to take a trap or enter Debug Mode. ISS golden models cannot natively model traps due to external stimulus, so Ibex relies on the RISCV-DV handshaking mechanism and a modified final-state register comparison to verify these scenarios.

Overview

In the Ibex end-to-end RTL/ISS co-simulation flow, an external stimulus refers to a triggering event that is not produced by the instruction stream itself but arrives from outside the core during execution. Typical examples of external stimulus in this context are:

  • Interrupts
  • Debug requests
  • Memory faults

Why ISS models cannot model external stimulus

The default trace-log comparison in the RTL/ISS co-simulation flow works by parsing register writebacks from both the core's trace log and the chosen golden-model instruction set simulator (ISS), and verifying that the core writes the correct data to the correct registers in the correct order. This approach is adequate for ordinary execution, but it falls apart when external stimulus is involved: while an ISS can simulate traps that result from in-program exceptions, it cannot model traps that result from external stimulus.

How Ibex verifies external-stimulus scenarios

To provide support for verifying that the core enters the proper interrupt handler, enters Debug Mode properly, and updates any CSRs correctly under external stimulus, Ibex relies heavily on the handshaking mechanism provided by the RISCV-DV instruction generator. This mechanism effectively allows the core to send status information to the testbench during program execution so that the testbench can perform runtime verification.

Key facts about this mechanism as used in Ibex:

  • The handshaking protocol itself is documented in the upstream RISCV-DV handshake documentation.
  • The signature address the Ibex testbench uses for the handshaking is 0x8ffffffc.
  • A small set of API tasks that integrate and use this mechanism in the Ibex environment is provided in core_ibex_base_test.sv.
  • Concrete examples of how the handshake is used during real simulations can be found in core_ibex_test_lib.sv.
  • The mechanism is extensively used to provide runtime verification for situations involving external debug requests, interrupt assertions, and memory faults.

Adapted trace-log comparison for external stimulus

In addition to the handshaking mechanism, a modified form of trace-log comparison is applied. A naive comparison of every register write during the whole simulation would produce false mismatches when external stimulus is involved, because the ISS trace log does not contain any execution information from the debug ROM or from any interrupt-handler code. Therefore, Ibex compares only the final values contained in every register at the end of the test. This works because any code executed in the debug ROM and trap handlers should not corrupt the register state used by the rest of the program.

Relationship to the broader flow

The complete end-to-end RTL/ISS co-simulation flow is controlled by the Makefile at dv/uvm/core_ibex/Makefile, and the verification of external-stimulus scenarios (via the RISCV-DV handshaking and the adapted final-state register comparison) is an integral part of that flow.

LINKED ENTITIES

3 links
interrupt PART_OF
debug request PART_OF
core_ibex_test_lib.sv USES

CITATIONS

4 sources
4 citations
[1] External stimulus (such as interrupts and debug requests) breaks the default register-writeback trace-log comparison because ISS models can simulate exception traps but cannot model traps due to external stimulus. Verification — Ibex Documentation
[2] Ibex uses the RISCV-DV instruction generator's handshaking mechanism, with signature address 0x8ffffffc, to let the core send status information to the testbench so it can verify correct interrupt handler entry, Debug Mode entry, and CSR updates under external stimulus. Verification — Ibex Documentation
[3] Integration API tasks for the handshake are provided in core_ibex_base_test.sv, and example usage of the handshake in real simulations is in core_ibex_test_lib.sv; the mechanism is extensively used to verify external debug requests, interrupt assertions, and memory faults. Verification — Ibex Documentation
[4] When external stimulus is involved, Ibex falls back to comparing only the final register values at the end of the test, because the ISS trace log does not contain execution information from the debug ROM or interrupt handler code, and those regions should not corrupt main-program register state. Verification — Ibex Documentation