debug request

Concept

A debug request is an external stimulus to the Ibex core that causes it to enter Debug Mode. In the Ibex verification environment, debug requests are among the external events that ISS-based golden models cannot directly simulate, so the testbench relies on the RISCV-DV handshaking mechanism and a modified register-state comparison to verify correct core behavior under debug request scenarios.

First seen 6/6/2026

Last seen 6/6/2026

Evidence 1 chunks

Wiki v1

WIKI

Definition

In the Ibex verification flow, a debug request is treated as a form of external stimulus to the core, alongside other asynchronous events such as interrupts. When a debug request is asserted, the core is expected to enter Debug Mode and update the relevant control/status registers (CSRs) accordingly.

Why ISS Co-Simulation Cannot Directly Check Debug Requests

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external stimulus ← part of 1e

Debug requests are a form of external stimulus in the co-simulation flow.

core_ibex_test_lib.sv ← uses 1e

core_ibex_test_lib.sv handles external debug request verification.

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core_ibex_test_lib.sv USES Extracted graph relationship

CITATIONS

7 sources

7 citations — click to expand

[1] A debug request is categorized as a form of external stimulus to the core, alongside interrupts. Verification — Ibex Documentation

[2] ISS models can simulate traps due to exceptions but cannot model traps due to external stimulus such as debug requests. Verification — Ibex Documentation

[3] The Ibex test environment uses the RISCV-DV handshaking mechanism so the core can send status information to the testbench, enabling verification that the core has entered Debug Mode properly and updated CSRs correctly when external debug requests occur. Verification — Ibex Documentation

[4] The signature address used by the Ibex testbench for the handshaking mechanism is 0x8ffffffc. Verification — Ibex Documentation

[5] The handshaking mechanism is extensively used in dv/uvm/core_ibex/tests/core_ibex_test_lib.sv to provide runtime verification for situations involving external debug requests, interrupt assertions, and memory faults. Verification — Ibex Documentation

[6] For simulations involving debug requests, only the final register values at the end of the test are compared between the core and ISS trace logs, because ISS models do not execute code in the debug ROM or trap handlers. Verification — Ibex Documentation

[7] The full verification flow that covers debug-request scenarios is controlled by the Makefile at dv/uvm/core_ibex/Makefile. Verification — Ibex Documentation