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Debug Request

Concept WIKI v1 · 6/6/2026

A debug request is an external stimulus to the Ibex core that causes it to enter Debug Mode. In the Ibex verification environment, debug requests are among the external events that ISS-based golden models cannot directly simulate, so the testbench relies on the RISCV-DV handshaking mechanism and a modified register-state comparison to verify correct core behavior under debug request scenarios.

Definition

In the Ibex verification flow, a debug request is treated as a form of external stimulus to the core, alongside other asynchronous events such as interrupts. When a debug request is asserted, the core is expected to enter Debug Mode and update the relevant control/status registers (CSRs) accordingly.

Why ISS Co-Simulation Cannot Directly Check Debug Requests

The end-to-end RTL/ISS co-simulation flow compares the trace log produced by the Ibex core against the trace log produced by a chosen golden-model ISS. Under normal execution the two logs are compared register writeback by register writeback to confirm that the correct data is written to the correct registers in the correct order.

This checking model is explicitly described as breaking down when situations involving external stimulus — including debug requests — are tested. ISS models can simulate traps due to architectural exceptions, but they cannot model traps due to external stimulus such as debug requests. As a result, the ISS trace log will not contain execution information for code run in the debug ROM or in any interrupt handler, and a naive per-writeback comparison would yield false mismatches.

How Debug Requests Are Verified

To support verification of external debug requests, the Ibex test environment relies on two complementary mechanisms:

  1. RISCV-DV handshaking mechanism. The core sends status information to the testbench during program execution, allowing the testbench to analyze whether the core has entered Debug Mode properly and updated the relevant CSRs. The signature address used by this testbench for the handshake is 0x8ffffffc. A small set of API tasks is provided in dv/uvm/core_ibex/tests/core_ibex_base_test.sv to integrate this mechanism, and the handshake is applied in dv/uvm/core_ibex/tests/core_ibex_test_lib.sv to provide runtime verification for situations involving external debug requests, interrupt assertions, and memory faults.

  2. Modified trace-log comparison. Rather than comparing every register writeback across the full simulation, only the final values contained in every register at the end of the test are compared. This avoids false mismatches caused by code executed in the debug ROM and trap handlers, on the assumption that such code should not corrupt register state elsewhere in the program.

Test Flow Control

The full verification flow, including the handling of debug-request scenarios, is orchestrated by the Makefile at dv/uvm/core_ibex/Makefile, which supports running single tests, full regressions, seeded runs with waveform dumps, verbose logging, parallel execution via LSF, assembly generation, and coverage-enabled regressions.

LINKED ENTITIES

2 links
external stimulus PART_OF
core_ibex_test_lib.sv USES

CITATIONS

7 sources
7 citations
[1] A debug request is categorized as a form of external stimulus to the core, alongside interrupts. Verification — Ibex Documentation
[2] ISS models can simulate traps due to exceptions but cannot model traps due to external stimulus such as debug requests. Verification — Ibex Documentation
[3] The Ibex test environment uses the RISCV-DV handshaking mechanism so the core can send status information to the testbench, enabling verification that the core has entered Debug Mode properly and updated CSRs correctly when external debug requests occur. Verification — Ibex Documentation
[4] The signature address used by the Ibex testbench for the handshaking mechanism is 0x8ffffffc. Verification — Ibex Documentation
[5] The handshaking mechanism is extensively used in dv/uvm/core_ibex/tests/core_ibex_test_lib.sv to provide runtime verification for situations involving external debug requests, interrupt assertions, and memory faults. Verification — Ibex Documentation
[6] For simulations involving debug requests, only the final register values at the end of the test are compared between the core and ISS trace logs, because ISS models do not execute code in the debug ROM or trap handlers. Verification — Ibex Documentation
[7] The full verification flow that covers debug-request scenarios is controlled by the Makefile at dv/uvm/core_ibex/Makefile. Verification — Ibex Documentation