Chisel HDL
ConceptChisel HDL (Constructing Hardware In a Scala Embedded Language) is a hardware description language embedded in Scala that brings object-oriented and functional programming, type-safety, and parameterization to hardware design. It is the implementation language of widely used open-source RISC-V cores such as Rocket and BOOM, compiles through the FIRRTL intermediate representation, and has been used for FPGA prototypes of RISC-V vector units. Its source-level type information is not preserved by mainstream open-source debugging tools, motivating format extensions such as Tywaves, and the FIRRTL compiler is itself reused by downstream tools (e.g., DIFUZZRTL) for register-coverage instrumentation.
First seen 5/28/2026
Last seen 6/9/2026
Evidence 15 chunks
Wiki v7
WIKI
Chisel HDL
Chisel HDL is a hardware description language (HDL) embedded in Scala that is used to implement open-source RISC-V processor designs, FPGA prototypes of vector architectures, and a variety of research hardware. In the evidence base for this article, Chisel HDL is characterized both through the processors that are written in it and through the tool-chain layer that supports it (in particular, the FIRRTL compiler).
Definition and language features
NEIGHBORHOOD
4 nodes · 4 edgesgraph · Chisel HDL · depth=1
RELATIONSHIPS
13 connectionsRocket Core is designed in Chisel HDL.
Chisel HDL is one of the Hardware Description Languages mentioned in the paper.
BOOM Core is designed in Chisel HDL.
Rocket is written in Chisel HDL.
BOOM is written in Chisel HDL.
Rocket Core is designed using Chisel HDL.
BOOM is designed in Chisel HDL.
RFUZZ is coupled to Chisel HDL.
RFUZZ is tightly coupled to Chisel HDL
Rocket Core is designed in Chisel HDL.
BOOM Core is designed in Chisel HDL.
Chisel is one of the HDLs used in the evaluated processors.
Chisel HDL uses FIRRTL as its intermediate representation, processed by the FIRRTL Compiler.
LINKED ENTITIES
5 linksFIRRTL Compiler USES Extracted graph relationship
Rocket Chip USED_TO_GENERATE DIFUZZRTL paper states 'Rocket core is an in-order pipelined core which is included in RISC-V Rocket Chip'; ProcessorFuzz paper states Rocket and BOOM 'can be generated using the Rocket Chip SoC Generator framework' and that this framework is the Chisel-based host of these cores.
DiFuzzRTL ENABLED_BY DIFUZZRTL's register-coverage instrumentation pass is implemented inside the FIRRTL compiler (2k lines of Scala) and is the primary consumer of the FIRRTL IR produced by Chisel HDL designs such as Rocket and BOOM.
RISC-V Rocket Core IMPLEMENTS Multiple sources describe Rocket as 'designed in Chisel HDL' and 'included in RISC-V Rocket Chip'.
RISC-V BOOM Core IMPLEMENTS ProcessorFuzz paper states BOOM 'is also designed in Chisel HDL' and 'can also be generated from the same Rocket Chip SoC Generator framework'.
CITATIONS
12 sources12 citations — click to expand
[1] Chisel stands for 'Constructing Hardware In a Scala Embedded Language' and is a broadly adopted HDL that brings object-oriented and functional programming, type-safety, and parameterization to hardware design. Tywaves: A Typed Waveform Viewer for Chisel
[2] Debugging Chisel designs with open source tools loses many of the advantages of the source language, as type information and data structure hierarchies are lost in the translation, simulator output, and waveform viewer. Tywaves: A Typed Waveform Viewer for Chisel
[3] DIFUZZRTL modified two different HDL processing tools: Pyverilog (for Verilog) and the FIRRTL compiler (for FIRRTL codes, which is the intermediate language of Chisel), to find control registers, instrument register-coverage, and produce instrumented Verilog code. DIFUZZRTL: Differential Fuzz Testing to Find RTL Bugs
[4] DIFUZZRTL's implementation of register-coverage instrumentation includes 1.5k lines of Python (in Pyverilog) and 2k lines of Scala (in the FIRRTL compiler). DIFUZZRTL: Differential Fuzz Testing to Find RTL Bugs
[5] Rocket core is an in-order pipelined core included in RISC-V Rocket Chip, supported by industry for chip prototyping, and extensively verified by the steering research group. DIFUZZRTL: Differential Fuzz Testing to Find RTL Bugs
[6] DIFUZZRTL's register coverage passes do not support SystemVerilog; they are tailored for FIRRTL, the intermediate representation used by Chisel HDL, which is the language in which Rocket and BOOM cores are designed. ProcessorFuzz: Processor Fuzzing with Control and Status Registers
[7] Rocket and BOOM cores can be generated using the Rocket Chip SoC Generator framework; Rocket is an in-order RISC-V core and BOOM is an out-of-order, superscalar RISC-V core, both designed in Chisel HDL, both taped out and capable of booting Linux. ProcessorFuzz: Processor Fuzzing with Control and Status Registers
[8] An attempt to convert BlackParrot's SystemVerilog to FIRRTL using Yosys failed due to limited support for SystemVerilog-to-FIRRTL conversion, leaving BlackParrot without register-coverage instrumentation. ProcessorFuzz: Processor Fuzzing with Control and Status Registers
[9] Tywaves contributions span the Chisel library and the CIRCT MLIR compiler, as well as the Surfer waveform viewer, producing a waveform viewer that better supports the Chisel HDL. Tywaves: A Typed Waveform Viewer for Chisel
[10] RFUZZ and the follow-up by Li et al. are highly coupled to Chisel HDL, which limits the applicability of those approaches to other HDLs. ProcessorFuzz: Processor Fuzzing with Control and Status Registers
[11] EARTH, a vector memory access architecture, is implemented on FPGA with Chisel HDL based on an open-source RISC-V vector unit, achieving 4x-8x speedups on strided-memory benchmarks while reducing hardware area by 9% and power consumption by 41%. Efficient Architecture for RISC-V Vector Memory Access
[12] DIFUZZRTL's register-coverage instrumentation overhead for synthetic RTL designs, measured as the percent increase in instrumented Verilog line count over the original, ranges from 24% (27-state design) down to 15% (216-state design). DIFUZZRTL: Differential Fuzz Testing to Find RTL Bugs