Chisel HDL

Concept

Chisel HDL (Constructing Hardware In a Scala Embedded Language) is a hardware description language embedded in Scala that brings object-oriented and functional programming, type-safety, and parameterization to hardware design. It is the implementation language of widely used open-source RISC-V cores such as Rocket and BOOM, compiles through the FIRRTL intermediate representation, and has been used for FPGA prototypes of RISC-V vector units. Its source-level type information is not preserved by mainstream open-source debugging tools, motivating format extensions such as Tywaves, and the FIRRTL compiler is itself reused by downstream tools (e.g., DIFUZZRTL) for register-coverage instrumentation. Surveyed RISC-V verification case studies additionally use Chisel HDL as a target for μGP-based functional/formal verification flows.

First seen 5/28/2026

Last seen 6/21/2026

Evidence 16 chunks

Wiki v8

WIKI

Chisel HDL

Chisel HDL is a hardware description language (HDL) embedded in Scala that is used to implement open-source RISC-V processor designs, FPGA prototypes of vector architectures, and a variety of research hardware. In the evidence base for this article, Chisel HDL is characterized both through the processors that are written in it and through the tool-chain layer that supports it (in particular, the FIRRTL compiler).

Definition and language features

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RELATIONSHIPS

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Rocket Core ← implements 100% 4e

Rocket Core is designed in Chisel HDL.

Hardware Description Language ← mentions 90% 2e

Chisel HDL is one of the Hardware Description Languages mentioned in the paper.

BOOM Core ← implements 100% 2e

BOOM Core is designed in Chisel HDL.

Rocket ← uses 100% 2e

Rocket is written in Chisel HDL.

BOOM ← uses 100% 2e

BOOM is written in Chisel HDL.

RISC-V Rocket Core ← implements 100% 2e

Rocket Core is designed using Chisel HDL.

BOOM ← implements 100% 2e

BOOM is designed in Chisel HDL.

RFUZZ ← implements 90% 2e

RFUZZ is coupled to Chisel HDL.

RFUZZ ← uses 95% 1e

RFUZZ is tightly coupled to Chisel HDL

Rocket Core ← implements 95% 1e

Rocket Core is designed in Chisel HDL.

BOOM Core ← implements 95% 1e

BOOM Core is designed in Chisel HDL.

Hardware Description Language part of → 100% 1e

Chisel is one of the HDLs used in the evaluated processors.

FIRRTL Compiler ← uses 100% 1e

Chisel HDL uses FIRRTL as its intermediate representation, processed by the FIRRTL Compiler.

Hardware Description Language (HDL) ← uses 85% 1e

Chisel HDL is used to implement a RISC-V ISA-based processor in HDL.

LINKED ENTITIES

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Hardware Description Language (HDL) USES Extracted graph relationship

CITATIONS

8 sources

8 citations — click to expand

[1] Chisel (Constructing Hardware In a Scala Embedded Language) is a broadly adopted HDL that brings object-oriented and functional programming, type-safety, and parameterization to hardware design. Tywaves: A Typed Waveform Viewer for Chisel

[2] Debugging Chisel designs with open source tools loses many of the advantages of the source language, as type information and data structure hierarchies are lost in the translation, simulator output, and waveform viewer. Tywaves: A Typed Waveform Viewer for Chisel

[3] Tywaves presents a new type-centered debugging format that brings the same level of abstraction found in contemporary hardware languages to waveform viewers, with contributions spanning the Chisel library and CIRCT MLIR compiler as well as the Surfer waveform viewer. Tywaves: A Typed Waveform Viewer for Chisel

[4] DIFUZZRTL modifies the FIRRTL compiler (the intermediate language of Chisel) with 2 k lines of Scala code to perform register-coverage instrumentation, alongside a 1.5 k-line Pyverilog-based Verilog path. DIFUZZRTL: Differential Fuzz Testing to Find RTL Bugs

[5] The Rocket core is an in-order pipelined core included in RISC-V Rocket Chip, supported by industry for chip prototyping, and extensively verified by the steering research group. DIFUZZRTL: Differential Fuzz Testing to Find RTL Bugs

[6] DIFUZZRTL reports register-coverage instrumentation overheads of 24%, 20%, 17%, and 15% for synthetic RTL designs with 27, 64, 125, and 216 states, respectively. DIFUZZRTL: Differential Fuzz Testing to Find RTL Bugs

[7] A surveyed verification case study targets a single-issue in-order, 32-bit, 5-stage RISC-V processor implemented in Chisel HDL using a μGP-driven, coverage-driven functional/formal methodology, achieving 93% total code coverage and finding 10 RTL-core bugs plus 1 reference-ISS bug, mainly in ISA and CSR handling, in less than 5 minutes. Survey of Verification of RISC-V Processors

[8] The EARTH vector memory access architecture is implemented on FPGA with Chisel HDL based on an open-source RISC-V vector unit, achieving 4x-8x speedups in benchmarks dominated by strided operations, and reducing hardware area by 9% and power consumption by 41% compared to conventional designs. Efficient Architecture for RISC-V Vector Memory Access