Chisel HDL

Chisel HDL is a hardware description language (HDL) embedded in Scala that is used to implement open-source RISC-V processor designs, FPGA prototypes of vector architectures, and a variety of research hardware. In the evidence base for this article, Chisel HDL is characterized both through the processors that are written in it and through the tool-chain layer that supports it (in particular, the FIRRTL compiler).

Definition and language features

Chisel is an acronym for Constructing Hardware In a Scala Embedded Language. It is described in the evidence as "a broadly adopted HDL that brings object-oriented and functional programming, type-safety, and parameterization to hardware design." These language features are reported to "significantly improve the process of writing code," but they also create a debugging gap: "debugging Chisel designs with open source tools loses many of the advantages of the source language, as type information and data structure hierarchies are lost in the translation, simulator output, and waveform viewer."

FIRRTL as the intermediate representation and compiler target

A key tool-chain fact established in the evidence is that Chisel HDL produces FIRRTL (Flexible Intermediate Representation for RTL) as its intermediate representation, and that the FIRRTL compiler is the natural place to attach HDL-processing passes to Chisel-generated designs. The DIFUZZRTL work states:

"We modified two different HDL processing tools: 1) Pyverilog, for codes written in Verilog [44]; and 2) FIRRTL compiler, for FIRRTL codes which is the intermediate language of Chisel [45]. These tools thus automatically find control registers, instrument register-coverage, then produce instrumented Verilog code as a final output. Our implementation includes 1.5 k lines of python code (in Pyverilog) and 2 k lines of the Scala code (in FIRRTL compiler)."

Processors designed in Chisel HDL

The open-source RISC-V Rocket core discussed in the DIFUZZRTL paper is written in Chisel HDL:

• RISC-V Rocket Core — described in the DIFUZZRTL paper as an in-order pipelined core that is "included in RISC-V Rocket Chip" and "supported by industry for the chip prototyping" and that "is extensively verified by the steering research group." The DIFUZZRTL differential-fuzzing evaluation uses a RISC-V reference model for comparison when fuzzing Rocket.

The same Rocket Chip framework is also the basis for FPGA prototypes of RISC-V vector units written in Chisel HDL, such as the EARTH vector memory access architecture.

Verification case studies on Chisel HDL designs

A 2025 survey of verification of RISC-V processors reports a case study on a single-issue in-order (SIIO), 32-bit, 5-stage RISC-V ISA-based processor implemented in Chisel HDL. The verification methodology applied to that core combines functional and formal methods through a μGP-driven, coverage-driven framework with three verification stages intended to detect bugs as early as possible in a pre-silicon ISA flow. Reported outcomes include 93% total code coverage, 10 bugs found in the RTL core and 1 bug in the reference ISS, with most of the bugs attributable to ISA and CSR handling and detected in less than 5 minutes. The survey characterizes the approach as having a low cost with no time-consuming hand-made testbenches, but notes high effort for formal and functional verification methods in complex designs.

Debugging tooling: Tywaves

The loss of source-level type information in simulation output and waveform viewers is identified as a practical obstacle for Chisel users. The Tywaves work contributes "a new type-centered debugging format that brings the same level of abstraction found in contemporary hardware languages to waveform viewers." The contributions span "the Chisel library and CIRCT MLIR compiler as well as the Surfer waveform viewer," with the stated goal of a "waveform viewer that better supports the Chisel HDL."

Role in the verification tool-chain

The evidence positions Chisel HDL — through its FIRRTL IR — as a precondition for the register-coverage class of processor-fuzzing guidance used in some prior work. DIFUZZRTL is described as a tool where its register-coverage instrumentation is "tailored for FIRRTL," and the DIFUZZRTL implementation modifies the FIRRTL compiler with "2 k lines of the Scala code" in addition to a Pyverilog-based Verilog path. DIFUZZRTL "monitors registers that directly or indirectly control multiplexer selection signals" as its guidance mechanism. The reported register-coverage instrumentation overheads for synthetic RTL designs, measured by the resulting instrumented Verilog line count, are approximately 15–24% over the unmodified design (24% for the 27-state version, decreasing to 15% for the 216-state version), as reported in the DIFUZZRTL coverage overhead table.

Use beyond processors

Outside the RISC-V core domain, the EARTH vector memory access architecture is "Implemented on FPGA with Chisel HDL based on an open-source RISC-V vector unit." In that work, Chisel HDL is used to describe a shifting-based memory subsystem that achieves "4x-8x speedups in benchmarks dominated by strided operations" and reduces hardware area by 9% and power consumption by 41% compared to conventional designs.

Scope limits

The evidence provided for this article does not describe:

• Chisel HDL's full syntax, type system, or the details of its embedding in Scala beyond the high-level claim that it brings OO/FP, type-safety, and parameterization.
• The complete compilation flow beyond the existence of a FIRRTL IR, the fact that the FIRRTL compiler is implemented in Scala, and mentions of CIRCT and MLIR in the context of Tywaves.
• FIRRTL's internal data model or individual transformations.
• Code-size, line-count, or general performance characteristics of Chisel HDL designs beyond the implementation size of the DIFUZZRTL FIRRTL pass (the reported area/power/throughput numbers are for the EARTH design, not for Chisel HDL itself).
• Bugs or fuzzing outcomes specific to Chisel HDL itself (the bugs reported in the evidence are bugs in Rocket or in a reference model, not in the HDL).

These topics are outside the scope of what the current source set supports.