Bug Detection

Concept

In the context of hardware implementation validation using tandem simulation, bug detection is the process of identifying design errors by cross-level comparison of architectural variables between a high-level instruction-level abstraction (ILA) model and a low-level RTL model. Instruction-by-instruction checking detects bugs substantially earlier than traditional run-to-the-end conformance testing.

First seen 6/6/2026

Last seen 6/6/2026

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Bug Detection

Overview

Bug detection in hardware verification refers to the identification of discrepancies between a high-level design specification and its low-level implementation. In the tandem simulation methodology described by Xing, Gupta, and Malik (ASPDAC 2022), bug detection is realized by comparing the architectural variables produced by an instruction-level execution model (ILEM) against those produced by an RTL-based execution model (RTEM). Any deviation between the two views is treated as a potential bug that can be localized by examining nearby instructions.

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Tandem Simulation ← uses 97% 2e

Tandem simulation enables earlier bug detection

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CITATIONS

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[1] In tandem simulation, an AV-Check at the end of each instruction compares ILAVs and RTAVs, and any deviation signifies a potential bug that can be analyzed with nearby instructions. Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models

[2] The AV-Check can also be invoked at specific intervals or checkpoints to reduce per-instruction comparison overhead. Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models

[3] The authors classify inserted bugs into three categories: condition bug (changes a value/condition in a conditional statement), data bug (changes a value in a computation), and expression bug (changes a logic operator such as AND/OR to XOR). Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models

[4] Tandem simulation often detects the bug earlier than finishing the test in conformance testing; in many cases the bug is found in less than 10% of the full test time, and in most cases in less than 40%. Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models

[5] An outlier in the bug detection study is a data bug in the FlexNLP design, where the buggy data is used only in a very late stage of the test program. Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models

[6] The instruction-by-instruction checking detects bugs earlier than run-to-the-end methods, which is one of the summarized experimental results. Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models

[7] AV-Swapping time from ILEM to RTEM is a one-time overhead that varies across designs and is determined roughly by the number of architectural variables and the cold-start length; it is negligible for tests with millions of instructions when not invoked very frequently. Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models

[8] Absolute simulation time for the traditional run-to-end conformance testing strategy ranges from 1 to 15 seconds for the design variants studied. Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models

[9] The case-study designs for bug detection evaluation include AES-block, AES-round, GB, FlexNLP, Pico, Piccolo, and Rocket Core. Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models