TestRIG
ToolTestRIG is an open-source framework/repository for randomized testing of RISC-V CPU implementations using RVFI-DII-style direct instruction injection and verification-engine trace checking. The provided evidence describes its use with QCVEngine, reduced counterexamples, CHERI-on-Ibex development, a Flute debugging case, and future directions such as richer generators and memory-concurrency testing.
First seen 5/27/2026
Last seen 6/8/2026
Evidence 23 chunks
Wiki v1
WIKI
Overview
TestRIG is presented in the paper Randomized Testing of RISC-V CPUs using Direct Instruction Injection as a RISC-V testing framework centered on open implementations, RVFI-DII-compatible components, and verification engines. The authors state that current TestRIG-compatible implementations and verification engines have been collated into an open-source TestRIG repository with documentation, and they expect TestRIG to contribute toward a standardized RISC-V testing framework that uses instrumentation of open implementations.
Verification approach
NEIGHBORHOOD
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50 connectionsTestRIG is used to verify CHERI security extensions on RISC-V processors.
QCVEngine is TestRIG's QuickCheck-based Verification Engine component.
TestRIG matures the approach of PyH2P, addressing its shortcomings.
TestRIG added Direct Instruction Injection to Spike emulator to use it as a reference implementation.
TestRIG uses the RVFI-DII interface as its standard interface for cross-verifying implementations.
TestRIG is compared against RISCV-DV as an alternative test generation framework.
TestRIG has been used to test Toooba, a superscalar out-of-order RISC-V processor.
TestRIG uses RVFI to observe execution traces from RISC-V implementations.
TestRIG is a framework designed to test RISC-V implementations.
TestRIG has been used to test the Flute RISC-V processor.
TestRIG implements model-based verification by comparing implementations against a formal Sail model.
TestRIG has been used to test the Piccolo RISC-V processor.
TestRIG has been used to test the Ibex RISC-V processor.
TestRIG uses a modular Verification Engine (VEngine) to stimulate implementations and compare traces.
TestRIG added Direct Instruction Injection to QEMU to use it as a reference implementation.
TestRIG evaluates architectural coverage using sailcov to measure branch coverage of the Sail RISC-V model.
TestRIG uses Direct Instruction Injection (DII) as a protocol for injecting instructions into RISC-V processors.
TestRIG uses the Sail RISC-V formal model as the golden reference for tandem execution.
TestRIG is explicitly compared to instruction-level unit tests and shown to replace them.
The paper introduces TestRIG as a testing framework for RISC-V implementations.
TestRIG uses Direct Instruction Injection to inject instruction sequences into RISC-V implementations.
The RISC-V golden Sail model implements RVFI-DII and is used within TestRIG for comparison.
TestRIG's model-based testing leads to counterexample-driven development.
TestRIG is used to test the Toooba processor, including CHERI extensions and lockup bugs.
TestRIG has completely replaced instruction-set level unit testing in the authors' development workflow.
TestRIG depends on a Verification Engine component to generate and compare instruction sequences.
TestRIG uses randomized instruction generation to produce test sequences.
TestRIG uses Direct Instruction Injection as its core mechanism for injecting instructions into CPU implementations.
TestRIG uses sailcov to measure architectural coverage of the Sail RISC-V model.
TestRIG uses tandem execution to compare execution traces between a model and an implementation.
TestRIG is used to validate correctness of the Flute CHERI implementation.
TestRIG compares execution traces to detect divergence between model and implementation.
TestRIG is used to validate correctness of the Piccolo CHERI implementation.
TestRIG uses RVFI-DII interfaces for direct instruction injection testing.
TestRIG has been used to test RVBS, a reference RISC-V implementation.
TestRIG uses RVFI-DII as its standardized communication interface.
TestRIG uses randomized instruction generation to produce test sequences.
QuickCheckVEngine is the verification engine used within the TestRIG infrastructure.
TestRIG supports annotating sequences as non-shrinkable to force initialization state coverage.
TestRIG checks equivalence between a model and implementation by executing the same sequences on both and comparing traces.
TestRIG uses the Sail RISC-V model as a reference model for tandem verification.
TestRIG implements tandem execution by running the same instruction sequences on both a model and an implementation and comparing traces.
TestRIG implements tandem verification by comparing execution traces of model and implementation.
TestRIG is effective at detecting pipeline bugs in RISC-V processors.
TestRIG uses counterexample shrinking to reduce failing test sequences to minimal examples.
TestRIG generates instruction sequences for testing RISC-V implementations.
TestRIG mentions pipeline verification as an application area, finding bugs in pipeline implementations.
TestRIG uses test case shrinking to reduce counterexamples to minimal failing cases.
TestRIG implements test case shrinking to reduce failing counterexamples to minimal sequences.
TestRIG is compared with riscv-tests in terms of coverage and counterexample complexity.
LINKED ENTITIES
32 linksRandomized Testing of RISC-V CPUs using Direct Instruction Injection INTRODUCES Extracted graph relationship
Direct Instruction Injection IMPLEMENTS Extracted graph relationship
Tandem Execution IMPLEMENTS Extracted graph relationship
Randomized Instruction Generation IMPLEMENTS Extracted graph relationship
RVFI-DII USES Extracted graph relationship
RVFI USES Extracted graph relationship
Execution Trace Comparison USES Extracted graph relationship
CHERI Security Extension EVALUATES Extracted graph relationship
RISC-V EVALUATES Extracted graph relationship
Test Case Shrinking USES Extracted graph relationship
Verification Engine (VEngine) USES Extracted graph relationship
Model-based Random Testing USES Extracted graph relationship
Tandem Verification USES Extracted graph relationship
Regression Testing USES Extracted graph relationship
Architectural Coverage USES Extracted graph relationship
RVBS EVALUATES Extracted graph relationship
Ibex EVALUATES Extracted graph relationship
Piccolo EVALUATES Extracted graph relationship
Flute EVALUATES Extracted graph relationship
Toooba EVALUATES Extracted graph relationship
Sail RISC-V Model USES Extracted graph relationship
spike USES Extracted graph relationship
QEMU USES Extracted graph relationship
Instruction Sequence Generation USES Extracted graph relationship
Counterexample-Driven Development IMPLEMENTS Extracted graph relationship
QCVEngine PART_OF Extracted graph relationship
PyH2P COMPARES_WITH Extracted graph relationship
Memory Concurrency Testing USES Extracted graph relationship
Pipeline Performance Testing USES Extracted graph relationship
Assertions in Instruction Sequences USES Extracted graph relationship
Non-shrinkable Sequences USES Extracted graph relationship
Sequence Import/Export IMPLEMENTS Extracted graph relationship
CITATIONS
11 sources11 citations — click to expand
[1] TestRIG-compatible implementations and verification engines were collated into an open-source TestRIG repository with documentation. Randomized Testing of RISC-V CPUs using Direct
[2] The authors expect TestRIG to contribute toward a standardized RISC-V testing framework using instrumentation of open implementations. Randomized Testing of RISC-V CPUs using Direct
[3] QCVEngine is described as the initial TestRIG verification engine, with Haskell generator infrastructure that supports rich and complex generators. Randomized Testing of RISC-V CPUs using Direct
[4] The evidence identifies future improvements to QCVEngine generators for virtual memory, cache testing, and floating-point operations. Randomized Testing of RISC-V CPUs using Direct
[5] Future memory-concurrency testing is described as injecting RVFI-DII instruction streams with specified timestamps into multiple shared-memory cores. Randomized Testing of RISC-V CPUs using Direct
[6] A more advanced verification engine would test RVFI traces for equivalence and against higher-level memory-model semantics. Randomized Testing of RISC-V CPUs using Direct
[7] A Flute bug was found after 42 tests and 20 rounds of shrinking; the reduced case involved overlapping memory operations, was found in under 10 seconds, and was fixed within an hour. Randomized Testing of RISC-V CPUs using Direct
[8] The Flute bug had escaped the development process, was not found by the RISC-V unit-test suite, and was difficult to debug from a full software trace. Randomized Testing of RISC-V CPUs using Direct
[9] TestRIG's model-based testing is described as leading to counterexample-driven development. Randomized Testing of RISC-V CPUs using Direct
[10] After Ibex was extended with RVFI-DII support, a summer intern added full CHERI functionality to Ibex in a month due to the reduced-counterexample loop provided by QCVEngine. Randomized Testing of RISC-V CPUs using Direct
[11] The evidence discusses a Sail-OCaml VEngine with direct access to Sail RISC-V model data structures to avoid independent encodings and support future template generation. Randomized Testing of RISC-V CPUs using Direct