Model-based Random Testing

Concept

Model-based random testing is a pragmatic verification approach in which randomly or directed-randomly generated test sequences are run against a reference model and an implementation, with execution traces compared to find divergences. In the RISC-V context, it is used when full formal equivalence of complex microarchitectures is difficult; it cannot prove equivalence, but it can refute it by producing counterexamples.

First seen 5/27/2026

Last seen 5/27/2026

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Overview

Model-based random testing is a functional verification technique that compares an implementation against a model while executing generated test sequences. In the cited RISC-V context, the approach is motivated by the difficulty of formally proving equivalence for complex microarchitectures. Rather than proving equivalence between a formal model and an implementation, model-based random testing can detect divergences and refute equivalence with counterexamples. [C1]

Method

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TestRIG ← uses 100% 2e

TestRIG is a model-based random testing tool that checks equivalence between a formal model and an implementation.

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CITATIONS

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[1] Model-based random testing detects divergence from a model and can refute, but not prove, equivalence between a formal model and an implementation. Randomized Testing of RISC-V CPUs using Direct

[2] Generated test programs are executed on both a golden model and a processor in development, with divergence typically detected by comparing execution traces. Randomized Testing of RISC-V CPUs using Direct

[3] Directed-random test-sequence generation has been used to debug pipeline and memory bugs and uncover unexpected implementation divergences; RISC-V generators include RISC-V RTG and RISCV-DV. Randomized Testing of RISC-V CPUs using Direct

[4] RISCV-DV generates RISC-V assembly programs for execution and includes RV32IMAFDC and RV64IMAFDC generators with support for page-table interactions, privileged CSR use, and traps or interrupts. Randomized Testing of RISC-V CPUs using Direct

[5] Formal RISC-V verification using RVFI tracing and tools such as JasperGold can prove trace equivalence in some cases, but is limited to in-order pipelines and requires specialist knowledge, so it does not yet replace functional testing for entire processors. Randomized Testing of RISC-V CPUs using Direct

[6] Randomly generated tests can produce long, convoluted counterexamples and must ensure useful instructions at randomly generated branch targets. Randomized Testing of RISC-V CPUs using Direct

[7] PyH2P applies automated test-case reduction to randomly generated RISC-V instruction sequences and often produces short, meaningful reproducing sequences, but has limitations in trace comparison, branch shrinking, and interface standardization. Randomized Testing of RISC-V CPUs using Direct

[8] TestRIG's Verification Engine stimulates RISC-V implementations over RVFI-DII sockets, injects instruction sequences, and compares execution traces until divergence; sequences may be loaded from disk, generated randomly, or produced by interactive architecture-driven exploration. Randomized Testing of RISC-V CPUs using Direct

[9] The cited TestRIG work compares executable formal models, software ISA simulators, and simulated hardware designs rather than completed fabricated chips, requiring a Direct Instruction Injection interface for tandem verification. Randomized Testing of RISC-V CPUs using Direct